Abstract
An architecture is presented for real-time continuous speech recognition based on a modified hidden Markov model. The algorithm is adapted to the needs of continuous speech recognition by efficient encoding of the state space, and logarithmic encoding of the weights so that products can be computed as sums. The paper presents the algorithm and its application related modifications, the mapping of the algorithm to a special purpose architecture, and the detailed design of this architecture using configurable logic. Emphasis is given on how the attributes of the algorithm are exploited in a configurable logic based design. A concrete design example is presented with a coprocessor engine having one large FPGA, 64 Mbytes of synchronous DRAM (SDRAM), a small FPGA as a SDRAM controller, and 2 Mbytes SRAM. This engine operating at 66 MHz performs roughly nine times as fast as a high end personal computer running a fully optimized version of the same algorithm.
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Stogiannos, P., Dollas, A. & Digalakis, V. A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 24, 223–240 (2000). https://doi.org/10.1023/A:1008197523254
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DOI: https://doi.org/10.1023/A:1008197523254