Abstract
It is known that any selection statement (e.g. if and switch-case statements) in an application is associated with a probability which could either be predetermined by user input or chosen at runtime. Such a statement can be regarded as a computation node whose computation time is represented by a random variable. This paper focuses on iterative applications (containing loops) reflecting those uncertainties. Such an application can then be transformed to a probabilistic data-flow graph.
Two timing models, the time-invariant and time-variant models, are introduced to characterize the nature of these applications. Since there can be many unfolding factors associated with each of the possible graph outcomes, for the time-invariant model, we propose a means of selecting a constant minimum rate-optimal unfolding factor for unfolding the probabilistic graph. We demonstrate that this factor guarantees the best schedule length.
We also suggest a good estimate for choosing an unfolding factor for a graph under the time-variant model. Experiments show that using our selection scheme results in an iteration period close to the theoretical iteration bound of the experimental graph. Furthermore, this paper discusses an alternative approach which selects a few optimal schedules (with respect to the graph outcomes) to be stored in the system. The other possibilities will be represented by a modified template graph.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
K.K. Parhi and D.G. Messerschmitt, “Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding,” Transactions on Computers, vol. 40, 1991, pp. 178–195.
A.A. Khan, C.L. McCreary, and M.S. Jones, “A Comparison of Multiprocessor Scheduling Heuristics,” in Proceedings of the 1994 International Conference on Parallel Processing, 1994, vol. II, pp. 243–250.
R.A. Kamin, G.B. Adams, and P.K. Dubey, “Dynamic List-Scheduling with Finite Resources,” in Proceedings of the 1994 International Conference on Computer Design (Cambridge, MA), Oct. 1994, pp. 140–144.
M.E. Wolfe and M.S. Lam, “A Loop Transformation Theory and an Algorithm to Maximize Parallelism,” IEEE Transactions on Parallel and Distributed Systems, vol. 2, 1991, pp. 452–471.
M.E. Wolfe, High Performance Compilers for Parallel Computing, Redwood City, CA: Addison-Wesley, 1996, ch. 9.
W. Li and K. Pingali, “A Singular Loop Transformation Framework Based on Non-Singular Matrices,” Tech. Rep. TR92-1294, Cornell University, Ithaca, NY, July 1992.
U. Banerjee, “Unimodular Transformations of Double Loops,” in Proceedings of the Workshop on Advances in Languages and Compilers for Parallel Processing, IEEE, Aug. 1990, pp. 192–219.
M. Lam, “Software Pipelining: An Effective Scheduling Technique for VLIW Machines,” in Proceedings of the ACM SIGPLAN’ 88 Conference on Programming Language Design and Implementation (Atlanta, GA), June 1988, pp. 318–328.
E.M. Girczyc, “Loop Winding–A Data Flow Approach to Functional Pipeline,” in Proceedings of the International Symposium on Circuits and Systems, May 1987, pp. 382–385.
C.E. Leiserson and J.B. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 6, 1991, pp. 5–35.
S. Dey, M. Potkonjak, and S.G. Rothweiler, “Performance Optimization of Sequential Circuits by Eliminating Retiming Bottlenecks,” in Proceedings of the 1992 IEEE/ACM International Conference on Computer Aided Design, 1992, pp. 504–509.
B. Lockyear and C. Ebeling, “The Practical Application of Retiming to the Design of High-Performance Systems,” in Proceedings of the 1993 IEEE/ACM International Conference on Computer Aided Design, 1993, pp. 288–295.
K.N. Lalgudi and M.C. Papaefthymiou, “DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling,” in Proceedings of the 32nd Design Automation Conference (San Francisco, CA), 1995, pp. 304–309.
L. Chao, A. LaPaugh, and E. Sha, “Rotation Scheduling: A Loop Pipelining Algorithm,” in Proceedings of the 30th Design Automation Conference (Dallas, TX), June 1993, pp. 566–572.
N.L. Passos, E. Sha, and S.C. Bass, “Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation,” in Proceedings of the 31st Design Automation Conference, June 1994, pp. 485–490.
L.-F. Chao and E.H.-M. Sha, “Retiming and Unfolding Data-Flow Graphs,” in Proceedings of the 1992 International Conference on Parallel Processing (St. Charles, IL), vol. II, IEEE, Aug. 1992, pp. 33–40.
D. Ku and G.D. Micheli, High-Level Synthesis of ASICS Under Timing and Synchronization Constraints, Kluwer Academic, 1992.
D. Ku and G.D. Micheli, “Relative Scheduling Under Timing Constraints: Algorithm for High-Level Synthesis,” IEEE transactions on CAD/ICAS, June 1992, pp. 697–718.
I. Karkowski and R.H.J.M. Otten, “Retiming Synchronous Circuitry with Imprecise Delays,” in Proceedings of the 32nd Design Automation Conference (San Francisco, CA), 1995, pp. 322–326.
L.A. Zadeh, “Fuzzy Sets as a Basis for a Theory of Possibility,” Fuzzy Sets and Systems, vol. 1, 1978, pp. 3–28.
M. Renfors and Y. Neuvo, “The Maximum Sampling Rate of Digital Filters Under Hardware Speed Constraints,” IEEE Transactions on Circuits and Systems, vol. CAS-28, 1981, pp. 196–202.
L.-F. Chao and E.H.-M. Sha, “Static Scheduling for Synthesis of DSP Algorithms on Various Models,” Journal of VLSI Signal Processing, vol. 10, 1995, pp. 207–223.
K. Mehlhorn, S. Näher, M. Seel, and C. Uhrig, LEDA User Manual Version 3.6.1. http://www.mpi-sb.mgp.de/LEDA
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Tongsima, S., O'Neil, T.W., Chantrapornchai, C. et al. Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 25, 215–233 (2000). https://doi.org/10.1023/A:1008187622838
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1008187622838