Abstract
This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel level parallelism is exploited in an FPGA design for the bottleneck portion of the application. The implementation of this design achieved a speedup of 21 compared to running on the host processor. The paper then describes an FPGA resource manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can be reconfigured for other purposes. The IR ATR application was ported to work with the RM and has been shown to adapt to the amount of reconfigurable hardware that is available at the time the application is executed.
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Jean, J., Liang, X., Drozd, B. et al. Automatic Target Recognition with Dynamic Reconfiguration. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 25, 39–53 (2000). https://doi.org/10.1023/A:1008173519198
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DOI: https://doi.org/10.1023/A:1008173519198