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Abstract

Two new low voltage transconductors are introduced and the statistical design of these transconductors are presented. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques are used as statistical VLSI design tools together with the statistical MOS (SMOS) model. The response surfaces obtained for the two transconductors show the trade-off between area and functional yield. Using these contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours also provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.

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References

  1. E.A. Vittoz, “Future of analog in the VLSI environment,” Proceedings 1990 IEEE International Symposium on Circuits and Systems, pp. 1372–1375, 1990.

  2. C. Michael and M. Ismail, Statistical Modeling for Computer-Aided Design of Analog MOS Integrated Circuits, Kluwer Academics Publishers, 1993.

  3. C. Michael and M. Ismail, “Statistical modeling of device mismatch for analog MOS integrated circuits,” IEEE JSSC, Vol. SC-27, pp. 154–166, 1992.

    Google Scholar 

  4. M. Ismail and T. Fiez, Analog VLSI Design and Signal Information Processing, McGraw-Hill, pp. 615–656, 1994.

  5. T.B. Tarim, H.H. Kuntman, and M. Ismail, “Statistical design techniques for yield enhancement of low voltage CMOS VLSI,” Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 2, Monterey, California, USA, May 1998.

    Google Scholar 

  6. T.B. Tarim, H.H. Kuntman, and M. Ismail, “Statistical design of a low voltage low power square-law CMOS cell,” Proceedings of the IEEJ, 2nd International Analog VLSI Workshop, ECT-98-30, Santa Clara, California, USA, pp. 81–85, June 1998.

  7. D.C. Montgomery, Design and Analysis of Experiments, Wiley, New York, 1997.

    MATH  Google Scholar 

  8. G.E.P. Box, Empirical Model Building and Response Surfaces, John Wiley & Son, 1987.

  9. H. Su, “Statistical design and optimization of engineering artifacts,” Ph.D. Dissertation, The Ohio State University, Columbus, 1995.

    Google Scholar 

  10. E. Seevinck and R.F. Wassenaar, “A versatile CMOS linear transconductor/square-law function circuit,” IEEE Journal of Solid-State Circuits, Vol. SC-22, pp. 366–377, June 1987.

    Article  Google Scholar 

  11. A. Motamed, “Low-Voltage Analog VLSI Circuits and Signal Processing,” Ph.D. Dissertation, The Ohio State University, Columbus, 1996.

    Google Scholar 

  12. A. Hyogo, C. Hwang, M. Ismail, and K. Sekine, “LV/LP CMOS square-law composite transistors for analog VLSI applications,” IEEJ 1'st International Analog VLSI Workshop, ECT-97-59, USA, pp. 139–143, May 1997.

  13. R.F.Wassenaar, Analysis of Analog CMOS Circuits, Oxford University Press, 1996.

  14. A. Nedungadi and T.R. Viswanathan, “Design of linear CMOS transconductance elements,” IEEE Transactions on Circuits and Systems, Vol. CAS-31, No. 10, pp. 891–894, October 1984.

    Article  Google Scholar 

  15. J.S. Martinez, M.J. Steyaert, and W.M.C. Sansen, “A largesignal very low-distortion transconductor for high-frequency continuous-time filters,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 7, pp. 946–955, 1991.

    Article  Google Scholar 

  16. F. Krummenacher and N. Joehl, “A 4 MHz CMOS continuoustime filter with on-chip automatic tuning,” IEEE Journal of Solid-State Circuits, Vol. SC-23, pp. 750–758, 1988.

    Article  Google Scholar 

  17. T.B. Tarim, “Statistical design techniques for yield enhancement of low voltage CMOS VLSI,” Ph.D. Dissertation, Istanbul Technical University, Istanbul, Turkey, submitted in 1998.

    Book  Google Scholar 

  18. Helsinki University of Technology, Circuit Theory Laboratory and Nokia Research Center, APLAC-An Object Oriented Analog Circuit Simulator and Design Tool, 7.1 User's Manual and Reference Manual, 1997.

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Tarim, T.B., Kuntman, H.H. & Ismail, M. Robust Design of Basic Low Voltage CMOS Transconductors. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 22, 87–102 (1999). https://doi.org/10.1023/A:1008139005510

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  • DOI: https://doi.org/10.1023/A:1008139005510

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