Abstract
While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.
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Schmit, H.H., Cadambi, S., Moe, M. et al. Pipeline Reconfigurable FPGAs. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 24, 129–146 (2000). https://doi.org/10.1023/A:1008137204598
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DOI: https://doi.org/10.1023/A:1008137204598