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A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays

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Abstract

A novel Space-Time Representation (STR) of iterative algorithms for their systematic mapping onto regular processor arrays is proposed. Timing information is introduced in the Dependence Graph (DG) by the definition and the construction of the Space-Time DG (STDG). Any variable instance of the loop body, independently of the number of the loop indices, is characterized by an integer vector composed by its indices, as space part, and an additional time index, representing its execution time according to a preliminary timing. The main advantage of the STR is that the need for the uniformization of the algorithm is avoided. Moreover, it is proven that in the STDG dependence vectors having opposite directions do not exist and therefore a linear mapping of the STDG onto the desired processor array can always be derived. Efficient 2D and 1D regular architectures are produced by applying the STR to the original description of the Warshall-Floyd algorithm for the Algebraic Path Problem.

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Authors and Affiliations

  1. Institute of Microelectronics, NCSR “DEMOKRITOS,”, Agia Paraskevi, 15310, Greece

    E.D. Kyriakis-Bitzaros

  2. VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110, Greece

    C.E. Goutis

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  1. E.D. Kyriakis-Bitzaros
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  2. C.E. Goutis
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Kyriakis-Bitzaros, E., Goutis, C. A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 22, 151–162 (1999). https://doi.org/10.1023/A:1008103504836

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