Abstract
Computation intensive DSP applications usually require parallel/pipelined processors in order to meet specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for such DSP applications. This algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool.
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References
R. M. Tomasulo, “An efficient algorithm for exploiting multiple arithmetic units,” IBM Journal of Research and Development, vol. 11, January 1967, pp. 25–33.
S. Davidson, D. Landskov, et al, “Some experiments in local microcode compaction for horizontal machines,” IEEE Transactions on Computers,” vol. c-30, July 1981, pp. 460–477.
D. D. Gajski, N. D. Dutt, A. C-H Wu, and S. Y-L Lin, High-Level Synthesis: Introduction to Chip and System Design, Boston: Kluwer Academic Publishers, 1992.
R. A. Kamin, G. B. Adams, and P. K. Dubey, “Dynamic list-scheduling with finite resources,” in International Conference on Computer Design, October 1994, pp. 140–144.
B. Shirazi et al, “PARSA: A PARallel program scheduling and assessment environment,” in International Conference on Parallel Processing, 1993.
P. D. Hoang and J. M. Rabaey, “Scheduling of DSP programs onto multiprocessors for maximum throughput,” IEEE Transactions on Signal Processing, vol. 41, June 1993.
S. Shukla and B. Little, “A compile-time technique for controlling real-time execution of task-level data-flow graphs,” in 1992 International Conference on Parallel Processing, vol. II, 1992.
R. B. Jones and V. H. Allan, “Software pipelining: an evaluation of enhanced pipelining,” in Proceedings of the 24th Annual International Symposium on Microarchitecture, vol. 24, 1991, pp. 82–92.
M. Lam, “Software pipelining,” in Proceedings of the ACM SIGPLAN'88 Conference on Progaming Language Design and Implementation, June 1988, pp. 318–328.
K. K. Parhi and D. G. Messerschmitt, “Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding,” in Proceedings of the International Conference on Parallel Processing, vol. I, 1989, pp. 209–216.
B. R. Rau. “Iterative modulo scheduling: an algorithm for software pipelining loops,” in Proc. 27th Annual International Symposium on Microarchtecture, November 1994, pp. 63–74.
J. L. Hennesy and D. A. Patterson, Computer Architecture A Quantitative Approach, California: Morgan and Kaufmann Publisher Inc., 1990.
A. A. Khan, C. L. McCreary, and M. S. Jones, “A comparison of multiprocessor scheduling heuristics, in 1994 International Conference on Parallel Processing, vol. II, IEEE, 1994, pp. 243–250.
P. M. Kogge, The Architecture of Pipelined Computers, New York: McGraw-Hill, 1981.
C. E. Leiserson and J. B. Saxe, “Retiming synchronous circuitry,” Algorithmica, June 1991, pp. 5–35.
L. Chao, A. LaPaugh, and E. Sha, “Rotation scheduling: a loop pipelining algorithm,” in Proceedings of ACM/IEEE Design Automation Conference, June 1993, pp. 566–572.
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Tongsima, S., Chantrapornchai, C., Sha, E.HM. et al. Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 18, 111–123 (1998). https://doi.org/10.1023/A:1008063207990
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DOI: https://doi.org/10.1023/A:1008063207990