Abstract
In this paper, a novel algorithm for low-power image coding and decoding is presented and the various inherent trade-offs are described and investigated in detail. The algorithm reduces the memory requirements of vector quantization, i.e., the size of memory required for the codebook and the number of memory accesses by using small codebooks. This significantly reduces the memory-related power consumption, which is an important part of the total power budget. To compensate for the loss of quality introduced by the small codebook size, simple transformations are applied on the codewords during coding. Thus, small codebooks are extended through computations and the main coding task becomes computation-based rather than memory-based. Each image block is encoded by a codeword index and a set of transformation parameters. The algorithm leads to power savings of a factor of 10 in coding and of a factor of 3 in decoding, at least in comparison to classical full-search vector quantization. In terms of SNR, the image quality is better than or comparable to that corresponding to full-search vector quantization, depending on the size of the codebook that is used. The main disadvantage of the proposed algorithm is the decrease of the compression ratio in comparison to vector quantization. The trade-off between image quality and power consumption is dominant in this algorithm and is mainly determined by the size of the codebook.
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J.M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1995.
A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.
S. Wuytack, F. Catthoor, F. Franssen, L. Nachtergaele, and H. DeMan, “Global communication and memory optimizing transformations for low-power systems,” Proc. of the International Workshop on Low-Power Design, pp. 203–208, 1994.
L. Nachtergaele, F. Catthoor, F. Balasa, F. Franssen, E. De Greef, H. Samsom, and H. DeMan, “Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems,” Proc. of the IEEE Intl. Workshop on Memory Technology, Design and Testing, San Jose, pp. 82–87, Aug. 1995.
A.Y. Wu and K.J.R. Liu, “A low-power and low complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion,” Proc. of IEEE ISCAS, pp. 155–158, 1994.
E. Scopa, A. Leone, R. Guerrieri, and G. Baccarani, “A 2D-DCT low-power architecture for H.261 coders,” Proc. of the IEEE ICASSP, pp. 3271–3274, 1995.
E.K. Tsern, A.C. Hung, and T.H.Y. Meng, “Video compression for portable communication using pyramid vector quantization of subband coefficients,” VLSI Signal Processing, Vol. 6, pp. 444–452.
A.P. Chandrakasan, A. Burstein, and R.W. Brodersen, “A low-power chipset for a portable multimedia I/O terminal,” IEEE Journal of Solid-State Circuits, Vol. 29, No.12, pp. 1415–1428, Dec. 1994.
A. Gersho and R.M. Gray, Vector Quantization and Signal Compression, Kluwer Academic Publishers, 1992.
Y. Linde, A. Buzo, and R.M. Gray, “An algorithm for vector quantizer design,” IEEE Trans. on Communications, Vol. 28, pp. 84–95, 1980.
Y.H. Hu, “Optimal VLSI architecture for vector quantization,” Proc. of the IEEE ICASSP, pp. 2853–2856, 1995.
J. Rabaey, L. Guerra, and R. Mehra, “Design guidance in the power dimension,” Proc. of the IEEE ICASSP, 1995.
M.F. Barnsley, Fractal Image Compression, A.K. Peters, 1994.
A.E. Jacquin, “Image coding based on fractal theory of iterative contractive image transformations,” IEEE Trans. on Image Processing, Vol. 1, pp. 18–30, Jan. 1992.
A. E. Jacquin “Fractal image coding: A review,” Proc. of the IEEE, Vol. 81, No.10, pp. 1451–1464, Oct. 1993.
M. Tartagni, A. Leone, A. Pirani, and R. Guerrieri, “A block-matching module for video compression,” Proc. of the IEEE Symposium on Low-Power Electronics, Digest of papers, pp. 24–25, 1994.
J.M. Rabaey, “Exploring the power dimension,” IEEE Custom Integrated Circuits Conference, pp. 215–220, 1996.
P. Landman, R. Mehra, and J.M. Rabaey, “An integrated CAD environment for low-power design,” IEEE Design and Test of Computers, pp. 72–82, Summer 1996.
D. Lidsky, J.M. Rabaey, “Early power exploration: A world wide web application,” Proc. of 33rd Design Automation Conference, Las Vegas, 1996.
P. Landman and J. Rabaey “Architectural power analysis: The dual bit type method,” IEEE Trans. on VLSI Systems, Vol. 3, No.2, pp. 173–187, June 1995.
H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Reading, MA, pp. 423–425, 1990.
R. San Martin and J.P. Knight, “Optimizing power in ASIC behavioral synthesis,” IEEE Design and Test of Computers, pp. 58–70, Summer 1996.
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Masselos, K., Merakos, P., Stouraitis, T. et al. Trade-Off Analysis of a Low-Power Image Coding Algorithm. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 18, 65–80 (1998). https://doi.org/10.1023/A:1007945427023
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DOI: https://doi.org/10.1023/A:1007945427023