Abstract
This paper presents a new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is useful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes together form the feasible solution space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explore various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible configurations, we adopt a simulated annealing approach to avoid being trapped in a local optimal configuration. This is complemented by a bi-partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of clock routing with zero-skew or a single fixed skew bound and separately sizing logic gates. This is achieved at no sacrifice of clock frequency.
Similar content being viewed by others
References
D. Dobberpuhl and R. Witek, “A 200 mhz 64b dual-issue cmos microprocessor,” in Proc. IEEE Intl. Solid-State Circuits Conf., pp. 106-107, 1992.
Joe G. Xi and Wayne W.M. Dai, “Buffer insertion and sizing under process variations for low power clock distribution,” in Proc. of 32nd Design Automation Conf., June 1995.
M.A.B. Jackson, A. Srinivasan, and E.S. Kuh, “Clock routing for high-performance ics,” in Proc. of 27th Design Automation Conf., pp. 573-579, 1990.
R.-S. Tsay, “An exact zero-skew clock routing algorithm,” IEEE Trans. on Computer-Aided Design, Vol. 12, No. 3, pp. 242-249, 1993.
T.H. Chao, Y.C. Hsu, J.M. Ho, K.D. Boese, and A.B. Kahng, ”Zero skew clock net routing,” IEEE Transactions on Circuits and Systems, Vol. 39, No. 11, pp. 799-814, Nov. 1992.
Qing Zhu, Wayne W.M. Dai, and Joe G. Xi, “Optimal sizing of high speed clock networks based on distributed rc and transmission line models,” in IEEE Intl. Conf. on Computer Aided Design, pp. 628-633, Nov. 1993.
N.-C. Chou and C.-K. Cheng, “Wire length and delay minimization in general clock net routing,” in Digest of Tech. Papers of IEEE Intl. Conf. on Computer Aided Design, pp. 552-555, 1993.
M. Edahiro, “A clustering-based optimization algorithm in zero-skew routings,” in Proc. of 30th ACM/IEEE Design Automation Conference, pp. 612-616, 1993.
Jun-Dong Cho and Majid Sarrafzadeh, “A buffer distribution algorithm for high-performance clock net optimization,” IEEE Transactions on VLSI Systems, Vol. 3, No. 1, pp. 84-97, March 1995.
S. Pullela, N. Menezes, J. Omar, and L.T. Pillage, “Skew and delay optimization for reliable buffered clock trees,” in IEEE Intl. Conf. on Computer Aided Design, pp. 556-562, 1993.
J.P. Fishburn, “Clock skewoptimization,” IEEE Transactions on Computers, Vol. 39, No. 7, pp. 945-951, 1990.
Joe G. Xi and Wayne W.M. Dai, “Low power design based on useful clock skews,” in Technical Report, UCSC-CRL-95-15, University of California, Santa Cruz., 1995.
J. Cong and C.K. Koh, “Minimum-cost bounded-skew clock routing,” in Proc. of Intl. Symp. Circuits and Systems, pp. 322- 327, 1995.
D.J.-H. Huang, A.B. Kahng, and C.-W.A. Tsao, “On the bounded-skew clock and steiner routing problems,” in Proc. of 32nd Design Automation Conf., pp. 508-513, 1995.
J. Cong, A.B. Kahng, C.K. Koh, and C.-W.A. Tsao, “Boundedskew clock and steiner routing under elmore delay,” in IEEE Intl. Conf. on Computer Aided Design, 1995 (to appear).
J.L. Neves and E.G. Friedman, “Design methodology for synthesizing clock distribution networks exploiting non-zero localized clock skew,” IEEE Transactions on VLSI Systems, June 1996.
W. Chuang, S.S. Sapatnekar, and I.N. Hajj, “A unified algorithm for gate sizing and clock skew optimization,” in IEEE Intl. Conference on Computer-Aided Design, pp. 220-223, Nov. 1993.
H. Sathyamurthy, S.S. Sapatnekar, and J.P. Fishburn, “Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization,” in IEEE Intl. Conference on Computer-Aided Design, Nov. 1995.
L. Kannan, Peter R. Suaris, and H.-G. Fang, “A methodology and algorithms for post-placement delay optimization,” in Proc. of 31th ACM/IEEE Design Automation Conference, pp. 327-332, 1994.
S. Kirkpatrick, Jr., C.D. Gelatt, and M.P. Vecchi, “Optimization by simulated annealing,” Science, Vol. 220, No. 4598, pp. 458- 463, May 1983.
Pak K. Chan, “Delay and area optimization in standard-cell design,” in Proc. of 27th Design Automation Conf., pp. 349-352, 1990.
Shen Lin and Malgorzata Marek-Sadowska, “Delay and area optimization in standard-cell design,” in Proc. of 27th Design Automation Conf., pp. 349-352, 1990.
Harry, V.M. Veendrick, “Short-circuit power dissipation of static cmos circuitry and its impact on the design of buffer circuits,” IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, Aug. 1984.
J. Rabae, D. Singh, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T.J. Mozdzen, “Power conscious cad tools and methodologies: A perspective,” Proceedings of IEEE, Vol. 83, No. 4, pp. 570-593, April 1995.
F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,” in Proc. of IEEE Intl. Symp. on Circuits and Systems, pp. 1929-1934, 1989.
National Semiconductor Corp. cs65 CMOS Standard Cell Library Data Book, National Semiconductor Corp., 1993.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Xi, J.G., Dai, W.WM. Useful-Skew Clock Routing with Gate Sizing for Low Power Design. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 16, 163–179 (1997). https://doi.org/10.1023/A:1007939023899
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1007939023899