This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.
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Y.C. Lim, “Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude,” IEEE Transactions on Circuits and Systems, Vol. 37, pp. 1480–1486, Dec. 1990.
H. Samueli, “An improved search algorithm for the design of multiplierless FIR filters with power-of-two coefficients,” IEEE Transactions on Circuits and Systems, Vol. 36, pp. 1044–1047, July 1989.
R. Jain, P.T. Yang, and T. Yoshino, “FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits,” IEEE Transactions on Signal Processing, Vol. 39, No. 7, pp. 1655–1667, 1991.
R.A. Hawley, B.C. Wong, T. Lin, J. Laskowski, and H. Samueli, ”Design techniques for silicon compiler implementations for high-speed FIR digital filters,” IEEE Journal of Solid-State Circuits, pp. 656–667, May 1996.
D.N. Pearson and K.K. Parhi, “Low-power FIR digital filter architectures,” in Proceedings of IEEE International Symposium on Circuits and Systems, Seattle, WA, May 1995, pp. 231– 234.
D.A. Parker and K.K. Parhi, “Area-efficient parallel FIR digital filter implementations,” in International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, Aug. 1996.
K.K. Parhi, “Trading off concurrency for low-power in linear and non-linear computations,” in Proceedings of the IEEE Workshop on Nonlinear Signal Processing, Halkidiki, Greece, June 1995, pp. 895–898.
K.K. Parhi, “Algorithms and architectures for high-speed and low-power digital signal processing,” in Proceedings of 4th International Conference on Advances in Communications and Control, Rhodes, Greece, June 1993, pp. 259–270.
A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-power CMOS digital design,” IEEE Journal of Solid-State Circuits, Vol. 27, pp. 473–483, April 1992.
P.P. Vaidyanathan, Multirate Systems and Filter Banks, Prentice Hall, Englewood Cliffs, NJ, 1993.
S. Winograd, “Arithmetic complexity of computations,” in CBMS-NSF Regional Conference Series in Applied Mathematics, SIAM Publications, No. 33, 1980.
Z.-J. Mou and P. Duhamel, “Short-length FIR filters and their use in fast nonrecursive filtering,” IEEE Transactions on Signal Processing, Vol. 39, pp. 1322–1332, June 1991.
Z.-J. Mou and P. Duhamel, “A unified approach to the fast FIR filtering algorithms,” in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, New York, NY, April 1988, pp. 1914–1917.
Z.-J. Mou and P. Duhamel, “Fast FIR filtering: Algorithms and implementations,” Signal Processing, Vol. 13, pp. 377–384, Dec. 1987.
H.K. Kwan and M.T. Tsim, “High speed 1-D FIR digital filtering architectures using polynomial convolution,” in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, Dallas, TX, April 1987, pp. 1863–1866.
A. Zergainoh and P. Duhamel, “Implementation and performance of composite fast FIR filtering algorithms,” in IEEE Signal Processing Society Workshop on VLSI Signal Processing, Sakai, Japan, pp. 267–276, Oct. 1995.
A.Y. Wu, K.J. Liu, Z. Zhang, K. Nakajima, A. Raghupathy, and S.C. Liu, “Algorithm-based low-power DSP system design: Methodology and verification,” in IEEE Signal Processing Society Workshop on VLSI Signal Processing, Sakai, Japan, Oct. 1995, pp. 277–286.
M. Srivastava and M. Potkonjak, “Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach,” in 33th ACM/IEEE Design Automation Conference, Las Vegas, NV, June 1996, pp. 343–348.
D. Li, J. Song, and Y.C. Lim, “A polynomial-time algorithm for designing digital filters with power-of-two coefficients,” in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 84–87, May 1993.
C.-L. Chen, K.-Y. Khoo, and A.N. Willson, Jr., “An improved polynomial-time algorithm for designing digital filters with power-of-two coefficients,” in Proceedings of IEEE International Symposium on Circuits and Systems, Seattle, WA, May 1995, pp. 84–87.
Y.C. Lim and S.R. Parker, “FIR filter design over a discrete powers-of-two coefficient space,” IEEE Transactions on Acoustics, Speech, and Signal Processing, pp. 583–591, June 1983.
Y.C. Lim and A.G. Constantinidies, “Linear phase FIR digital filter without multipliers,” in Proceedings of IEEE International Symposium on Circuits and Systems, Tokyo, Japan, July 1983, pp. 185–188.
Y.C. Lim and B. Liu, “Design of cascade form FIR filters with discrete valued coefficients,” IEEE Transactions on Acoustics, Speech, and Signal Processing, pp. 1735–1739, Nov. 1988.
R.W. Reitwiesner, “Binary arithmetic,” in Advances in Computers, Academic, Vol. 1, pp. 231–308, 1966.
A. Chatterjee, R.K. Roy, and M.A. d'Abreu, “Greedy hardware optimization for linear digital circuits using number splitting and refactorization,” IEEE Transactions on VLSI Systems, Vol. 1, pp. 423–431, Dec. 1993.
R.I. Hartley and K.K. Parhi, Digit-Serial Computation, Kluwer Academic Publishers, Norwell, MA, 1995.
M. Potkonjak, M.B. Srivastava, and A. Chandrakasan, “Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching,” in DAC-94, Proceedings of the 31st ACM/IEEE Design Automation Conference, pp. 189–194, 1994.
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Parker, D.A., Parhi, K.K. Low-Area/Power Parallel FIR Digital Filter Implementations. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 17, 75–92 (1997). https://doi.org/10.1023/A:1007901117408
- Finite Impulse Response
- Hardware Cost
- Finite Impulse Response Filter
- Maximum Absolute Difference
- Canonic Signed Digit