Abstract
We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.
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Bednara, M., Teich, J. Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing 26, 149–165 (2003). https://doi.org/10.1023/A:1024447517501
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DOI: https://doi.org/10.1023/A:1024447517501