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An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters

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Abstract

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper, a formula is derived that describes accurately the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

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Authors and Affiliations

  1. Department of Electrical Engineering, K.U. Leuven, ESAT-MICAS, Kard. Mercierlaan 94, B-3001, Heverlee, Belgium

    Anne van den Bosch, Michiel Steyaert & Willy Sansen

Authors
  1. Anne van den Bosch
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  2. Michiel Steyaert
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  3. Willy Sansen
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Bosch, A.v.d., Steyaert, M. & Sansen, W. An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters. Analog Integrated Circuits and Signal Processing 29, 173–180 (2001). https://doi.org/10.1023/A:1011261330190

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  • DOI: https://doi.org/10.1023/A:1011261330190

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