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Design Automation for Embedded Systems

, Volume 4, Issue 4, pp 329–351 | Cite as

FACE: Fine-tuned Architecture Codesign Environment for ASIP Development

  • I-Horng Jeng
  • Feipei Lai
  • Yuh-Dar Tseng
Article

Abstract

High-performance, reliable, and robust products with a short development schedule are general design aims. FACE was developed to achieve these goals, including the organization of a design flow, a frequency-driven information analyzer, compiler techniques (code generator and instruction optimization), and a hierarchical object design library. This paper explores the design space of a retargetable compiler and a reconfigurable hardware, which combine both software and hardware reprogrammability. The environment, FACE, we have developed allows us to quickly move the functions between software and hardware in a state of flux. Finally, it generates the application specific integrated processor (ASIP) and a compiler for the new ASIP architecture. The case study is considered which demonstrates the efficiency in ASIP design of FACE.

Code Generator Retargetable Compiler Hardware Library 

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Copyright information

© Kluwer Academic Publishers 1999

Authors and Affiliations

  • I-Horng Jeng
    • 1
  • Feipei Lai
    • 1
  • Yuh-Dar Tseng
    • 2
  1. 1.Dept. of Electrical EngineeringNational Taiwan UniversityTaipeiTaiwan, R.O.C
  2. 2.VIA Technologies, INC.TaipeiTaiwan, R.O.C

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