Advertisement

Design Automation for Embedded Systems

, Volume 4, Issue 4, pp 243–310 | Cite as

A Petri Net Model for Hardware/Software Codesign

  • Paulo Maciel
  • Edna Barros
  • Wolfgang Rosenstiel
Article

Abstract

This work presents Petri nets as an intermediate model for hardware/software codesign. The main reason of using of Petri nets is to provide a model that allows for formal qualitative and quantitative analysis in order to perform hardware/software partitioning. Petri nets as an intermediate model allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper highlights methods of computing load balance, mutual exclusion degree and communication cost of behavioral description in order to perform the initial allocation and the partitioning. This work is also devoted to describing a method for estimating hardware area, and it also presents an overview of the general partitioning method considering multiple software components.

Petri nets hardware/software codesign quantitative analysis estimation 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    A. A. Desrochers, R. Y. Al-Jaar. Applications of Petri Nets in Manufacturing Systems. IEEE Press, 1995.Google Scholar
  2. 2.
    R. Gupta. A framework for interative analysis of timing constraints in embedded systems. Proceedings of the Fourth Codes/CASHE, pp. 44-51, IEEE Computer Society, March 1996.Google Scholar
  3. 3.
    A. Dasdan, D. Ramanathan, R. Gupta. Rate derivation and its applications to reactive, real-time embedded systems. 35th ACM Design Automation Conference, pp. 44-51, June 1998.Google Scholar
  4. 4.
    W. Wolf. Object-oriented cosynthesis of distributed embedded systems. 35th ACM Transactions on Design Automation of Electronic Systems 1(3): 301-314, July 1996.Google Scholar
  5. 5.
    S. Gaubert, J. Mairesse. Modeling and analysis of timed Petri nets using heaps of pieces LIAFA, CNRS-Université Paris 7 — Report 97/14, 1997.Google Scholar
  6. 6.
    Y. Kukimoto, R. Brayton. Exact required time analysis via false path detection. ACM Design Automation Conference, 1997.Google Scholar
  7. 7.
    F. Vahid, D. D. Gajski. Closeness metrics for systems leel functional partitioning. Proceedings of the EURO-DAC'95 pp. 328-333, IEEE Computer Society, September 1995.Google Scholar
  8. 8.
    D. D. Gajski, F. Vahid. Specification and design of embedded systems. Design and Test of Computers 53-67, Spring 1995.Google Scholar
  9. 9.
    D. D. Gajski, F. Vahid, S. Narayan, J. Gong. Specification and Design of Embedded Hardware-Software Systems. P T R Prentice Hall, 1994.Google Scholar
  10. 10.
    T. BenIsmail, M. Abid, K. O'Brien and A. Jerraya. An approach for hardware/software codesign. Proceedings of the RSP 94, Grenoble, France, 1994.Google Scholar
  11. 11.
    P.V. Knudsen and J. Madsen. PACE: A dynamic programming algorithm for hardware/software partitioning. Fourth International Workshop on HW/SW Codesign, pp. 85-92, IEEE Press, 1996.Google Scholar
  12. 12.
    C. Carreras, J. C. López, M. L. López, C. Delgado-Kloos, N. Martinéz, and L. Sánchez. A co-design methodology based on formal specification and high-level estimation. Fourth International Workshop on HW/SW Codesign, pp. 28-35, IEEE Press, 1996.Google Scholar
  13. 13.
    T. Cheung, G. Hellestrand and P. Kanthamanon. A multi-level transformation approach to HW/SW codesign: A case study. Fourth International Workshop on HW/SW Codesign, pp. 10-17, IEEE Press, 1996.Google Scholar
  14. 14.
    E. Barros. Hardware/Software Partitioning Using UNITY. Universität Tübingen, 1993.Google Scholar
  15. 15.
    E. Barros and W. Rosenstiel. A clustering approach to support hardware/software partitioning. In Jerzy Rozenblit and Klaus Buchenrieder, editors, Computer Aided Software/Hardware Engineering, IEEE Press.Google Scholar
  16. 16.
    E. Barros and A. Sampaio. Towards provably correct hardware/software partitioning using occam. Proceedings of the Third International Workshop on Hardware/Software Codesign Codes/CASHE94, IEEE Computer Society, September 1994.Google Scholar
  17. 17.
    E. Barros, X. Xiong and W. Rosenstiel. Hardware/software partitioning with UNITY. Handouts of International Workshop on Hardware-Software Co-design, 1993.Google Scholar
  18. 18.
    R. Ernst and J. Henkel. Hardware-software codesign of embedded controllers based on hardware extraction. Handouts of the International Workshop on Hardware-Software Co-Design, October 1992.Google Scholar
  19. 19.
    R. Ernst and J. Henkel. A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. IEEE/ACM Proc. of 8th Int'l Symp. on System Level Synthesis, October 1995.Google Scholar
  20. 20.
    R. Gupta and G. De Micheli. System-level synthesis using re-programmable components. Microprogramming and Microprocessing 27: 239-244, 1989.Google Scholar
  21. 21.
    C. Carreras, J. C. López, M. L. López, C. Delgado-Kloos, N. Martínez, L. Sánchez. A co-design methodology based on formal specification and high level estimation. Proceedings of EDAC, pp. 2-7, 1996.Google Scholar
  22. 22.
    F. Rose, T. Carpenter, S. Kumar, J. Shackleton, T. Steeves. A model for the coanalysis of hardware and software architecture. Proceedings of the Fourth Codes/CASHE, pp. 94-103, IEEE Computer Society, March 1996.Google Scholar
  23. 23.
    R. Gupta, G. De Micheli. Constrained software generation for hardware-software systems. Proceedings of the Fourth Codes/CASHE, pp. 56-63, IEEE Computer Society. September 1995.Google Scholar
  24. 24.
    P. Eles, K. Kuchcinki, Z. Peng, M. Minea. Synthesis of VHDL concurrent processes. Proceedings of the EURO-DAC'94, pp. 540-545, IEEE Computer Society, September 1994.Google Scholar
  25. 25.
    X. Gu, K. Kuchcinki, Z. Peng. Testability analysis and improvement from VHDL behavioural specification. Proceedings of the EURO-DAC'94, pp. 644-649, IEEE Computer Society, September 1994.Google Scholar
  26. 26.
    G. W. Brams. Réseaux de Petri: Théorie et Pratique, tome 1. Masson Editions, 1983.Google Scholar
  27. 27.
    G. W. Brams. Réseaux de Petri: Théorie et Pratique, tome 2. Masson Editions, 1983.Google Scholar
  28. 28.
    J. L. Peterson. Petri Nets an Introduction. Prentice-Hall, Inc, 1981.Google Scholar
  29. 29.
    W. Reisig. Petri Nets: An Introduction. Springer-Verlag, 1982.Google Scholar
  30. 30.
    T. Murata. State equation, controllability, and maximal of Petri nets. IEEE Trans. on Automatic Control, 1977.Google Scholar
  31. 31.
    T. Murata. Modelling and Analysis of Concurrent Systems, Handbook of Software Engineering. Van Norstrand Reinhold Company Inc., 1984.Google Scholar
  32. 32.
    O. Botti, F. Cindio. From basic to timed net models of occam: An application to program placement. PNPM, pp. 216-221, 1991.Google Scholar
  33. 33.
    M. Silva, E. Teruel. Petri nets for the design and operation of manufacturing systems. CIMAT'96, 1996.Google Scholar
  34. 34.
    M. Silva, E. Teruel. Analysis of autonomous Petri nets with a bulk services and arrivals. 11th International Conference on Analysis and Optimization of Systems. Discrete Event Systems, Vol. 199 of Lecture Notes in Control and Information Science, pp. 131-143, 1994.Google Scholar
  35. 35.
    A. Valmari. Stubborn sets for reduced state space generation. Advanced in Petri Nets. In G. Rozenberg, editor, Lecture Notes in Computer Science 483: 491-515, Springer Verlag, 1991.Google Scholar
  36. 36.
    A. Valmari. Compositional state space generation. Advanced in Petri Nets. In G. Rozenberg, editor, Lecture Notes in Computer Science 674: 427-457, Springer Verlag, 1993.Google Scholar
  37. 37.
    T. Murata. Petri nets: Properties, analysis and applications. Proceeding of the IEEE, 1989.Google Scholar
  38. 38.
    G. Berthelot. Checking properties of nets using transformations. Advanced in Petri Nets. In G. Rozenberg, editor, Lecture Notes in Computer Science 222: 19-40, Springer Verlag, 1986.Google Scholar
  39. 39.
    K. Jensen. Coloured Petri nets: Basic concepts, analysis methods and practical uses. EACTS Monographs on Theoretical Computer Science. Springer Verlag, 1994.Google Scholar
  40. 40.
    I. Gorton. Parallel program design using high-level Petri nets. Concurrency: Practice and Experience, 1993.Google Scholar
  41. 41.
    G. Dohmen. Petri nets as intermediate representation between VHDL and symbolic transition systems. Proceedings EURODAC-94, 1994.Google Scholar
  42. 42.
    J. Esparza, M. Nielsen. Decidability issues for Petri nets. Gesellschaft für Informatik, 1994.Google Scholar
  43. 43.
    C. Rackoff. The covering and boundedness problem for vector addition systems. Theoretical Computer Science 6: 223-231, 1978.Google Scholar
  44. 44.
    R. Karp, R. Miller. Parallel program schemata. Journal of Computer and System Science 3(4): 167-195, 1969.Google Scholar
  45. 45.
    R. Lipton. The reachability problem requires exponential space. Research Report 62, Department of Computer Science, Yale University, 1976.Google Scholar
  46. 46.
    G. S. Sacerdote, R. L. Tenney. The decidibility of the reachability problem for vector addition system. 9th Annual Symposium on Theory of Computing, 61-76.Google Scholar
  47. 47.
    E. W. Mayr. Persistence of vector replacement system is decidable. Acta Informatica 15: 309-318, 1981. Boulder, 1977.Google Scholar
  48. 48.
    S. R. Kosaraju. Decidibility of reachability in vector addition systems. 14th Annual ACM Symposium on Theory of Computing, San Francisco, 1982, pp. 267-281.Google Scholar
  49. 49.
    J. L. Lambert. Vector addition systems and semi-linearity. SIAM Journal of Computing, 1994.Google Scholar
  50. 50.
    D. Frutos, C. Johne. Decidability of home states in place transition systems. 14th Internal Report, Dpto. Informatica y Automatica, Univ. Complutense de Madrid, 1986.Google Scholar
  51. 51.
    E. Cardoza, R. J. Lipton, A. R. Meyer. Exponential space complete problems for Petri nets and commutative semigroups. 8th Symposium on Theory of Computing, 50-54, 1976.Google Scholar
  52. 52.
    M. H. T. Hack. Decidability Questions for Petri Nets. PhD Thesis, MIT, 1976.Google Scholar
  53. 53.
    A. Cheng, J. Esparza, J. Palsberg. Complexity results for 1-safe nets. 13th Conference on Foundations of Software Technology and Theoretical Computer Science, Bombay, 1993.Google Scholar
  54. 54.
    J. Grabowsky. The decidability of persistence for vector addition systems. Information Processing Letters 11 1: 20-23, 1980. 76.block Boulder, 1977.Google Scholar
  55. 55.
    H. Müller. On the reachability problem for persistent vector replacement systems. Computing Supplements 3: 89-104, 1981.Google Scholar
  56. 56.
    K. Jensen. Coloured Petri nets: A high level language for system design and analysis. Lecture Notes in Computer Science 483: 342-416, 1990.Google Scholar
  57. 57.
    Ramchandani. Analysis of asynchronous concurrent systems by timed Petri nets. Technical Report n 120, Laboratory for Computer Science, MIT, Cambridge, MA, 1974.Google Scholar
  58. 58.
    K. Jensen, P. Huber, R. M. Shapiro. Hierarchies in coloured Petri nets. In G. Rozenberg, editor, Lecture Notes in Computer Science 483: 313-341, Springer-Verlag, 1990.Google Scholar
  59. 59.
    P. R. M. Maciel, E. N. S. Barros. Captura de requisitos temporais usando redes de Petri para o particionamento de hardware/software. IX Simpósio Brasileiro de Concepção de Circuitos Integrados, Recife, PE, 1996, pp. 383-396.Google Scholar
  60. 60.
    C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall International, 1985.Google Scholar
  61. 61.
    P. R. M. Maciel, E. N. S. Barros. Capturing time constraints by using Petri nets in the context of hardware/software codesign. a ser publicado no 7th IEEE International Workshop on Rapid System Prototyping, Porto Caras, Thessaloniki, Grécia, 1996.Google Scholar
  62. 62.
    G. Jones. Programming in OCCAM. C. A. R. Hoare Series Editor, Prentice-Hall International Series in Computer Science, 1987.Google Scholar
  63. 63.
    L. Silva, A. Sampaio and E. Barros. A normal form reduction strategy for hardware/software partitioning. Conference Formal Methods Europe'97, 1997.Google Scholar
  64. 64.
    P. R. M. Maciel, R. D. Lins, P. R. F. Cunha. Uma Introdução às Redes de Petri e Aplicações. Book published in the 11th Escola de Computação. Campinas, Brazil. July, 1996. (portuguese)Google Scholar
  65. 65.
    W. W. Chu, L. J. Holloway, M.T. Lang, K. Efe. Task allocation in distributed data processing. IEEE-Computer 57-68, November 1980.Google Scholar
  66. 66.
    V. M. Lo. Heuristic algorithms for task assignment is distributed systems. IEEE Transactions on Computers 37(11): 1384-1397, November 1988.Google Scholar
  67. 67.
    C. E. Houstis. Module allocation of real-time applications to distributed systems. IEEE Transactions on Software Engineering 5(7): 699-709, July 1990.Google Scholar
  68. 68.
    W. W. Chu, L. M-T. Lan. Task allocation and precedence relations for distributed real-time systems. IEEE Transactions on Computers C-36(6): 667-679, June 1987.Google Scholar
  69. 69.
    P. Maciel, E. Barros, W. Rosenstiel. Computing communication cost by Petri nets for hardware/software codesign. 8th IEEE International Workshop on Rapid System Prototyping, Chapel Hill, North Carolina, June 24–26, 1997.Google Scholar
  70. 70.
    P. Maciel, E. Barros, W. Rosenstiel. Using Petri nets to compute communication cost for hardware/software codesign. Published on the 10th Brazilian Symposium on Integrated Circuit Design, Gramado, Rio Grande do Sul, Brazil, August 25–27, 1997.Google Scholar
  71. 71.
    P. M. Merlin, D. J. Farber. Recoverability of communication protocols implications of a theoretical study. IEEE Transaction Communication COM-24, September 1976.Google Scholar
  72. 72.
    P. Maciel, T. Maciel, E. Barros, W. Rosenstiel. A Petri net approach to compute load balance in hardware/software codesign. High Performance Computing '98, Boston, Massachusetts, April 5–9, 1998.Google Scholar
  73. 73.
    P. Maciel, E. Barros, W. Rosenstiel. A Petri net approach for quantifying mutual exclusion degree. INCOM'98, Nancy-Metz, France, June 23–27, 1998.Google Scholar
  74. 74.
    P. Maciel, E. Barros, W. Rosenstiel. A Petri net based approach for performing the initial allocation in hardware/software codesign. 1998 IEEE International Conference on Systems, Man, and Cybernetics, San Diego, October 11–14, 1998.Google Scholar
  75. 75.
    P. Maciel, E. Barros, W. Rosenstiel. A Petri net approach to compute load balance in hardware/software codesign. To be published on the High Performance Computing '99, San Diego, April 1999.Google Scholar
  76. 76.
    N. G. Leveson, J. L. Stolzy. Safety analysis using Petri nets. IEEE Transaction Software Eng. SE-13(3): March 1987.Google Scholar
  77. 77.
    W. M. Zubarek. Timed Petri nets definitions, properties and applications. Microelectronic and Reliability 31(4): 627-644, 1991.Google Scholar
  78. 78.
    P. H. Starke. Remarks on timed Petri nets. Proc. 9th European Workshop on Application and Theory of Petri Nets, 1988.Google Scholar
  79. 79.
    M. Ajmone-Marsan. Stochastic Petri nets: An elementary introduction. LNCS vol. 424, Springer Verlag, 1989.Google Scholar
  80. 80.
    M. K. Molloy. On the Integration of Delay and Throughput Measures in Distributed Processing Models. Ph.D. Thesis, UCLA, Los Angeles, CA, 1981.Google Scholar
  81. 81.
    S. Gaubert. Performance evaluation of (max, +) automata. IEEE Transaction on Automatic Control, 1995.Google Scholar
  82. 82.
    C. Ghezzi, D. Mandrioli, S. Morasca, M. Pezz. A unified high-level Petri net formalism for time-critical systems. IEEE Transactions on Software Engineering, February 1991.Google Scholar
  83. 83.
    J. Sifakis. Use of Petri nets for performance evaluation. Measuring, Modelling and Evaluating Computer Systems, North Holland, 1977.Google Scholar
  84. 84.
    J. M. Colom, M. Silva. Convex geometry and semiflows in P/T nets. A comparative study of algorithms for computation of minimal P-semiflows. In G. Rozenberg, editor, Lecture Notes in Computer Science 483: 79-112, Springer-Verlag, 1990.Google Scholar
  85. 85.
    F. Bowden. Modeling time in Petri nets. 2th Australia-Japan Workshop on Stochastic Models, Gold Coast, July 1996.Google Scholar
  86. 86.
    J. M. Colom, M. Silva. Improving the linearly based characterization of P/T nets. In G. Rozenberg, editor, Lecture Notes in Computer Science 483: 113-145, Springer-Verlag, 1990.Google Scholar
  87. 87.
    F. Dicesare, G. Harhalakis, J. M. Proth, M. Silva, F. B. Vernadat. Practice of Petri Nets in Manufacturing. Chapman and Hall, 1993.Google Scholar
  88. 88.
    M. Zhou, F. Dicesare. Petri Net Synthesis for Discrete Event Control of Manufacturing Systems. Kluwer Academic Publishers, 1993.Google Scholar
  89. 89.
    C. Lindemann. Performance Modelling with Deterministic and Stochastic Petri Nets. John Wiley and Sons, 1998.Google Scholar
  90. 90.
    S. Malik, M. Martonosi, Yau-Tsun L. Static timing analysis of embedded software. Design Automation Conference, 1997.Google Scholar
  91. 91.
    F. Ercal, J. Ramanuajam, P. Sadayappan. Task allocation onto a hypercube by recursive minicut bipartitioning. Journal of Parallel and Distributed Computing 10: 35-44, 1990.Google Scholar
  92. 92.
    C. Cohen, S. Gaubert, J. Quadrat. Algebraic system analysis of timed Petri nets. In J. Gunawardena, editor, Idempotency — Collection of Isaac Newton Institute, Cambridge University Press, 1995.Google Scholar
  93. 93.
    R. Spencer and A. Sampaio. De occam para o Transputer: Compilação via Reescrita de Termos. Anais do X Simpósio Brasileiro de Engenharia de Software, São Carlos-SP, 1996, pp. 103-117.Google Scholar
  94. 94.
    M. E. de Lima and D. J. Kinniment. Hierarchial placement method based on a force-directed algorithm and simultaneous global routing for sea-of-gates. IEE Proceedings, Computing. Digit. Tech. 143(1): 1-8, January 1996.Google Scholar
  95. 95.
    K. A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. Vicentelli, A. Wang. Multilevel logic minimization using implicit don't cares. IEEE Transactions on CAD 7(6), June 1988.Google Scholar
  96. 96.
    R. Camposano, W. Rosenstiel. Synthesizing circuits from behavioral descriptions. IEEE Transactions on CAD of Integrated Circuits and Systems 8(2): 171-180, February 1989.Google Scholar
  97. 97.
    G. Borriello. Combining event and data flow graphs in behavioral synthesis. Proceeding of the ICCAD, pp. 56-59, 1988.Google Scholar
  98. 98.
    D. De Micheli, D. Ku, F. Mailhot and T. Trunong. The Olympus Synthesis System. IEEE Design and Test of Computers, October 1990.Google Scholar

Copyright information

© Kluwer Academic Publishers 1999

Authors and Affiliations

  • Paulo Maciel
    • 1
  • Edna Barros
    • 1
  • Wolfgang Rosenstiel
    • 2
  1. 1.Departamento de InformáticaUniversidade de PernambucoRecifeBrazil
  2. 2.Fakultaet fuer InformatikUniversitaet TuebingenTuebingenGermany

Personalised recommendations