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Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems

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Abstract

Wepresent the Serra Run-Time Scheduler Synthesis and AnalysisTool which automatically generates a run-time scheduler froma heterogeneous system-level specification in both Verilog HDLand C. Part of the run-time scheduler is implemented in hardware,which allows the scheduler to be predictable in being able tomeet hard real-time constraints, while part is implemented insoftware, thus supporting features typical of software schedulers. Serra's real-time analysis generates a priority assignment forthe software tasks in the mixed hardware-software system. Thetasks in hardware and software have precedence constraints, resourceconstraints, relative timing constraints, and a rate constraint.A heuristic scheduling algorithm assigns the static prioritiessuch that a hard real-time rate constraint can be predictablymet. Serra supports the specification of critical regions insoftware, thus providing the same functionality as semaphores.We describe the task control/data-flow extraction,synthesis of the control portion of the run-time scheduler inhardware, real-time analysis and priority scheduler template.We also show how our approach fits into an overall tool flowand target architecture. Finally, we conclude with a sample applicationof the novel run-time scheduler synthesis and analysis tool toa robotics design example.

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332-0250

    Vincent John Mooney III

  2. Computer Systems Laboratory, Stanford University, Gates Computer Science Building, Stanford, CA, 94305

    Giovanni De Micheli

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  1. Vincent John Mooney III
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  2. Giovanni De Micheli
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Mooney, V.J., Micheli, G.D. Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems. Design Automation for Embedded Systems 6, 89–144 (2000). https://doi.org/10.1023/A:1008941525972

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