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A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

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Abstract

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over complete automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been used to build good-quality compilers for three fixed-point DSPs.

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References

  1. A. Aho, M. Ganapathi, and S. Tjiang. Code Generation Using Tree Matching and Dynamic Programming. ACM Transactions on Programming Languages and Systems, 11(4):491-516, October 1989.

    Article  Google Scholar 

  2. A. Aho, R. Sethi, and J. Ullman. Compilers Principles, Techniques and Tools. Addison-Wesley, 1986.

  3. G. Araujo and S. Malik. Optimal Code Generation for Embedded Memory Non-Homogeneous Register Architectures. In Proceedings of 8th International Symposium on System Synthesis, pages 36-41, 1995.

  4. G. Araujo, A. Sudarsanam, and S. Malik. Instruction Set Design and Optimization for Address Computation in DSP Architectures. In Proceedings of 9th International Symposium on System Synthesis, pages 102-107, 1996.

  5. P. Briggs, K.D. Cooper, and L. Torczon. Improvements to Graph Coloring Register Allocation. ACM Transactions on Programming Languages and Systems, 16(3):428-455, May 1994.

    Article  Google Scholar 

  6. A. Fauth. Beyond Tool-Specific Machine Descriptions. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, chapter 8, pages 138-152. Kluwer Academic Publishers, 1995. ISBN 0-7923-9577-8.

  7. C.W. Fraser, D.R. Hanson, and T.A. Proebsting. Engineering a Simple, Efficient Code-Generator Generator. ACM Letters of Programming Languages and Systems, 1(3):213-226, September 1992.

    Article  Google Scholar 

  8. C. Gebotys. DSP Address Optimization Using a Minimum Cost Circulation Technique. In Proceedings of the International Conference on Computer-Aided Design, pages 100-103, November 1997.

  9. M.X. Goemans and D.P. Williamson. Improved approximation algorithms for maximum cut and satisfiability problems using semidefinite programming. Journal of the ACM, 42:1115-1145, 1995.

    Article  MATH  MathSciNet  Google Scholar 

  10. G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Proceedings of the 34th Design Automation Conference, pages 299-302, June 1997.

  11. D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable Code Generation for Embedded DSP Processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, chapter 5, pages 85-102. Kluwer Academic Publishers, 1995. ISBN 0-7923-9577-8.

  12. R. Leupers, A. Basu, and P. Marwedel. Optimized Array Index Computation in DSP Programs. In Proceedings of the Asia-Pacific Design Automation Conference, pages 87-92, February 1998.

  13. R. Leupers and P. Marwedel. Algorithms for Address Assignment in DSP Code Generation. In Proceedings of the International Conference on Computer-Aided Design, pages 109-112, 1996.

  14. R. Leupers and P. Marwedel. Instruction Selection for Embedded DSPs with Complex Instructions. In Proceedings of the European Design Automation Conference, pages 200-205, 1996.

  15. S. Liao, S. Devadas, K. Keutzer, and S. Tjiang. Instruction Selection Using Binate Covering for Code Size Optimization. In Proceedings of the International Conference on Computer-Aided Design, pages 393-399, 1995.

  16. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang. Storage Assignment to Decrease Code Size. In ACM Transactions on Programming Languages and Systems, volume 18, pages 235-253, May 1996.

    Article  Google Scholar 

  17. P. Marwedel. The MIMOLA Design System: Tools for the Design of Digital Processors. In Proceedings of the 21st Design Automation Conference, pages 587-593, 1997.

  18. Motorola. DSP56000/DSP56001 Digital Signal Processor User's Manual. 1990.

  19. P.G. Paulin, C. Liem, T.C. May, and S. Sutarwala. CodeSyn: A Retargetable Code Synthesis System. In Proceedings of the 7th International Symposium on High-Level Synthesis, page 94, April 1994.

  20. M.A.R. Saghir, P. Chow, and C.G. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. In Proceedings of the ACM SIGARCH Conference on Architectural Support for Programming Languages and Operating Systems, pages 234-243, 1996.

  21. A. Sudarsanam and S. Malik. Memory Bank and Register Allocation in Software Synthesis for ASIPs. In Proceedings of the International Conference on Computer-Aided Design, pages 388-392, 1995.

  22. Ashok Sudarsanam. Code Optimization Libraries for Retargetable Compilation for Embedded Digital Signal Processors. PhD thesis, Princeton University, November 1998.

  23. Texas Instruments. TMS320C2x User's Guide. January 1993. Revision C.

  24. V. Živojnović, J. Martínez Velarde, and C. Schläger. DSPstone: A DSP-oriented Benchmarking Methodology. Technical report, Aachen University of Technology, August 1994.

  25. B. Wess. Automatic Instruction Code Generation Based on Trellis Diagrams. In Proceedings of the International Symposium on Circuits and Systems, pages 645-648, 1992.

  26. B. Wess and M. Gotschlich. Constructing Memory Layouts for Address Generation Units Supporting Offset 2 Access. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, pages 683-686, 1997.

  27. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S.-W. Liao, C.-W. Tseng, M. Hall, M. Lam, and J. Hennessy. SUIF: A Parallelizing and Optimizing Research Compiler. Technical report, CSL-TR-94-620, Stanford University, May 1994.

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Authors and Affiliations

  1. Department of Electrical Engineering, Princeton University, Princeton, NJ, USA

    Ashok Sudarsanam & Sharad Malik

  2. Fujitsu Laboratories of America, Santa Clara, CA, USA

    Masahiro Fujita

Authors
  1. Ashok Sudarsanam
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  2. Sharad Malik
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  3. Masahiro Fujita
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Sudarsanam, A., Malik, S. & Fujita, M. A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Design Automation for Embedded Systems 4, 187–206 (1999). https://doi.org/10.1023/A:1008913323623

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