Journal of Electronic Testing

, Volume 16, Issue 5, pp 419–426 | Cite as

LFSR-Based Deterministic TPG for Two-Pattern Testing

  • Xiaowei Li
  • Paul Y.S. Cheung
  • Hideo Fujiwara


This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.

built-in self-test two-pattern test configurable LFSR path delay faults 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    K. Furuya and E.J. McClusky, “Two Pattern Test Capability of Autonomous TPG Circuits,” Proc. of IEEE 1991 Int'l Test Conf. (ITC'91), pp. 704-711.Google Scholar
  2. 2.
    S. Pilarski and A. Pierzyriska, “BIST and Delay Fault Detection,” Proc. of IEEE 1993 Int'l Test Conf. (ITC'93), pp. 236-242.Google Scholar
  3. 3.
    I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis, “Accumulator-Based BIST Approach for Stuck-Open and Delay Fault Testing,” Proc. of IEEE 1995European Design and Test Conf. (EURO DTC'95), pp. 431-435.Google Scholar
  4. 4.
    P. Girard, C. Landrault, V. Moreda, and S. Pravossoudovitch, “An Optimized BIST Test Pattern Generator for Delay Testing,” Proc. of IEEE 1997VLSI Test Symposium (VTS'97), pp. 94-100.Google Scholar
  5. 5.
    X. Li and P.Y.S. Cheung, “Exploiting BIST Approach for Two-Pattern Testing,” Proc. of IEEE 1998 Asian Test Symp. (ATS'98), pp. 424-429.Google Scholar
  6. 6.
    C.A. Chen and S.K. Gupta, “BIST Test Pattern Generators for Two-Pattern Testing: Theory and Design Algorithms,” IEEE Trans. on Computers, Vol. 45, No. 3, pp. 257-269, 1996.Google Scholar
  7. 7.
    C. Dufaza and Y. Zorian, “On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs,” Proc. of IEEE 1997 European Design and Test Conf. (EURODTC'97), pp. 69-76.Google Scholar
  8. 8.
    C.W. Starke, “Built-In Test for CMOS Circuits,” Proc. of IEEE 1984 Int'l Test Conf. (ITC'84), pp. 309-314.Google Scholar
  9. 9.
    B. Wurth and K. Fuchs, “A BIST Approach to Delay Fault Testing with Reduced Test Length,” Proc. of IEEE 1995 European Design and Test Conf. (ET & DC'95), pp. 418-423.Google Scholar
  10. 10.
    S.W. Golomb, L.R. Welch, R.M. Goldstein, and A.W. Hales, Shift Register Sequences, Aegean Park Press, 1982.Google Scholar
  11. 11.
    C.J. Shi and J.A. Brzozowski, “Cluster-Cover: A Theoretical Framework for a Class of VLSI-CAD Optimization Problem,” ACM Trans. on Design Automation of Electronic Systems, Vol. 3, No. 1, pp. 76-107, 1998.Google Scholar
  12. 12.
    F. Brglez, D. Bryan, and K. Kozminski, “Combinational Pro-file of Sequential Benchmark Circuits,” Proc. of IEEE 1989 Int'l Symposium on Circuits and Systems (ISCAS'98), pp. 1929-1934.Google Scholar
  13. 13.
    S. Devadas and K. Keutzer, “An Algorithmic Approach to Optimizing Fault Coverage for BIST Logic Synthesis,” Proc. of IEEE 1998 Int'l Test Conf. (ITC'98), pp. 164-173.Google Scholar
  14. 14.
    S. Zhang, R. Byrne, and D.M. Miller, “BIST Generators for Sequential Faults,” Proc. of IEEE 1992 Int'l Conf. on Computer Design (ICCD'92), pp. 260-263.Google Scholar

Copyright information

© Kluwer Academic Publishers 2000

Authors and Affiliations

  • Xiaowei Li
  • Paul Y.S. Cheung
  • Hideo Fujiwara

There are no affiliations available

Personalised recommendations