Journal of Electronic Testing

, Volume 16, Issue 5, pp 553–566 | Cite as

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency

  • Satoshi Ohtake
  • Toshimitsu Masuzawa
  • Hideo Fujiwara


This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low.

non-scan design for testability complete fault efficiency controllers at-speed test 


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Copyright information

© Kluwer Academic Publishers 2000

Authors and Affiliations

  • Satoshi Ohtake
  • Toshimitsu Masuzawa
  • Hideo Fujiwara

There are no affiliations available

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