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Journal of Electronic Testing

, Volume 20, Issue 4, pp 333–344 | Cite as

Datapath BIST Insertion Using Pre-Characterized Area and Testability Data

  • J.C. Wang
  • P.S. Cardoso
  • J.A.Q. Gonzalez
  • M. Strum
  • R. Pires
Article
  • 37 Downloads

Abstract

There are several ways to insert Built-in Self-Test (BIST) circuitry on a circuit, each of them with particular consequences on area overhead, test application time and fault coverage. This paper presents a BIST insertion methodology applied to datapaths described at the RTL level that uses a database containing: (a) testability data of several types of test pattern generators (TPGs) and signature analyzers (SAs) when connected to several types of functional units and (b) area overhead due to the implementation by a datapath register of each type of those test resources. The availability of this database makes then possible to choose the best test resource types associated to each functional unit in a datapath, leading to good testability and area results.

test library self-test RTL architecture pre-computed testability 

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References

  1. 1.
    M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, Revised Printing, IEEE Press, 1990.Google Scholar
  2. 2.
    L. Avra, "Allocation and Assignment in High Level Synthesis for Self-testable Data Paths," in Proceedings of the International Test Conference, 1991, pp. 463–472.Google Scholar
  3. 3.
    D. Berthelot, M.L. Flottes, and B. Rouzeyre, "BISTing Data Paths at Behavioral Level," in Proceedings of the International Test Conference, 2000, pp. 672–679.Google Scholar
  4. 4.
    D. Berthelot, M.L. Flottes, and B. Rouzeyre, "A Method for Trading-Off Test Time, Area and Fault Coverage in Datapath BIST Synthesis," Journal of Electronic Testing (JETTA), vol. 17, nos. 3/4, pp. 331–339, 2001.Google Scholar
  5. 5.
    P.S. Cardoso, M. Strum, J.R.A. Amazonas, and J.C. Wang, "A Methodology for Minimum Area Cellular Automata Generation," in Proceedings of the Seventh IEEE Asian Test Symposium, Singapore, 1998, pp. 33–37.Google Scholar
  6. 6.
    C. Gebotys and M.I. Elmasry, Optimal VLSI Architectural Synthesis: Area, Performance and Testability, Norwell, MA, Kluwer Academic Publishers, 1992.Google Scholar
  7. 7.
    D. Gizopoulos, A. Paschalis, and Y. Zorian, "An Effective BIST Scheme for Datapaths," in Proceedings of the International Test Conference, 1996, pp.76–85.Google Scholar
  8. 8.
    I. Gosh and N. Jha, "A BIST Scheme for RTL Circuits Based on Symbolic Testability Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, pp. 111–128.Google Scholar
  9. 9.
    H. Harmanani and C.A. Papachristou, "An Improved Method for RTL Synthesis with Testability Tradeoffs," IEEE ICCAD, 1993, pp. 30–35.Google Scholar
  10. 10.
    P.D. Hortencius, R.D. McLeod, W. Pries, D.M. Miller, and H.C. Card, "Cellular Automata-Based Pseudorandom Number Generators for Built-in Self-Test," IEEE Transactions on Computer-Aided Design, vol. 8, no. 8, pp. 842–859, 1989.Google Scholar
  11. 11.
    A. Jas, C.V. Crishna, and N.A. Touba, "Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme," in Proceedings of the 19th IEEE VLSI Test Symposium, 2001, pp. 2–8.Google Scholar
  12. 12.
    N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis, and Y. Zorian, "Power/Energy-Efficient BIST Schemes for Processsor Data Paths," IEEE Design and Test, Oct.-Dec. 2000, pp. 15–28.Google Scholar
  13. 13.
    N. Nicolici and Bashir M. Al-Hashimi, "Tackling Test Tradeoffs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation," in Proceedings of the International Test Conference, 2001, pp. 72–81.Google Scholar
  14. 14.
    A. Orailoglu and I.G. Harris, "Microarchitectural Synthesis for Rapid BIST Testing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 6, pp. 573–586, 1997.Google Scholar
  15. 15.
    C. Papachristou and J. Carletta, "Test Synthesis in the Behavioral Domain," in Proceedings of the International Test Conference, 1995, pp. 693–702.Google Scholar
  16. 16.
    I. Parulkar, S.K. Gupta, and M.A. Breuer, "Introducing Redundant Computation in a Behavior for Reducing BIST Resources," in Proceedings of the Design Automation Conference, 1998, pp. 275–278.Google Scholar
  17. 17.
    M. Psarakis, D. Gizopoulos, A.M. Paschalis, and Y. Zorian, "Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1083–1099, 2000.Google Scholar
  18. 18.
    M. Serra, T. Slater, J.C. Muzio, and D.M. Miller, "The Analysis of One Dimensional Linear Cellular Automata and Their Aliasing Properties," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 7, pp. 767–778, 1990.Google Scholar
  19. 19.
    A.P. Stroele and H.-J. Wunderlich, "Hardware-Optimal Test Register Insertion," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 6, pp. 531–539, 1998.Google Scholar

Copyright information

© Kluwer Academic Publishers 2004

Authors and Affiliations

  • J.C. Wang
    • 1
  • P.S. Cardoso
    • 1
  • J.A.Q. Gonzalez
    • 1
  • M. Strum
    • 1
  • R. Pires
    • 2
  1. 1.Electronic Systems DepartmentEscola Politécnica da Universidade de São PauloBrazil
  2. 2.Technological CenterUniversidade Cruzeiro do SulBrazil

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