Design Automation for Embedded Systems

, Volume 8, Issue 2–3, pp 249–265 | Cite as

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications

  • Prabhat Mishra
  • Nikil Dutt
  • Hiroyuki Tomiyama

Abstract

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. A significant bottleneck in the validation of such systems is the lack of a golden reference model. Thus, many existing techniques employ a bottom-up approach to architecture validation, where the functionality of an existing pipelined architecture is, in essence, reverse-engineered from its implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through Architecture Description Language (ADL) constructs, and thus allows a powerful top–down approach to architecture validation. The most important requirement in top–down validation process is to ensure that the specification (reference model) is golden. Earlier, we have developed validation techniques to ensure that the static behavior of the pipeline is well-formed by analyzing the structural aspects of the specification using a graph based model. In this paper, we verify the dynamic behavior by analyzing the instruction flow in the pipeline using a Finite State Machine (FSM) based model to validate several important architectural properties such as determinism and in-order execution in the presence of hazards and multiple exceptions. We applied this methodology to the specification of a representative pipelined processor to demonstrate the usefulness of our approach.

Architecture specification determinism in-order execution pipeline validation 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Halambi, A. et al. EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability. Design Automation and Test in Europe (DATE), pp. 485-490, 1999.Google Scholar
  2. 2.
    Jacobi, C. Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving. Computer Aided Verification (CAV), pp. 309-323, 2002.Google Scholar
  3. 3.
    Cyrluk, D. Microprocessor Verification in PVS: A Methodology and Simple Example. Technical Report, SRI-CSL-93-12, 1993.Google Scholar
  4. 4.
    Hadjiyiannis, G. et al. ISDL: An Instruction Set Description Language for Retargetability. Design Automation Conference (DAC), pp. 299-302, 1997.Google Scholar
  5. 5.
    Burch, J. et al. Automatic Verification of Pipelined Microprocessor Control. Computer Aided Verification (CAV), pp. 68-80, 1994.Google Scholar
  6. 6.
    Huggins, J. and D. Campenhout. Specification and Verification of Pipelining in the ARM2 RISC Microprocessor. ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 3,no. 4, pp. 563-580, October 1998.Google Scholar
  7. 7.
    Hennessy, J. and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc, 1990.Google Scholar
  8. 8.
    Levitt, J. and K. Olukotun. Verifying Correct Pipeline Implementation for Microprocessors. International Conference on Computer-Aided Design (ICCAD), p. 162-169, 1997.Google Scholar
  9. 9.
    Sawada, J. and W. D. Hunt. Processor Verification with Precise Exceptions and Speculative Execution. Computer Aided Verification (CAV), pp. 364-375, 1998.Google Scholar
  10. 10.
    Skakkebaek, J. and R. Jones, and D. Dill. Formal Verification of Out-of-Order Execution Using Incremental Flushing. Computer Aided Verification (CAV), pp. 98-109, 1998.Google Scholar
  11. 11.
    Aagaard, M., B. Cook, N. Day, and R. Jones. A Framework for Microprocessor Correctness Statements. Correct Hardware Design and Verification Methods (CHARME), pp. 433-448, 2001.Google Scholar
  12. 12.
    Freericks, M. The nML Machine Description Formalism. Technical Report TR SM-IMP/DIST/08, TU Berlin CS Dept., 1993.Google Scholar
  13. 13.
    Srivas, M. and M. Bickford. Formal Verification of a Pipelined Microprocessor. IEEE Software, vol. 7,no. 5, pp. 52-64, 1990.Google Scholar
  14. 14.
    Velev, M. and R. Bryant. Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction. Design Automation Conference (DAC), pp. 112-117, 2000.Google Scholar
  15. 15.
    Ho, P. et al. Formal Verification of Pipeline Control Using Controlled Token Nets and Abstract Interpretation. International Conference on Computer-Aided Design (ICCAD), pp. 529-536, 1998.Google Scholar
  16. 16.
    Mishra, P. et al. Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications. CECS TR 03-25, University of California, Irvine, 2003.Google Scholar
  17. 17.
    Mishra, P. et al. Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units. Design Automation and Test in Europe (DATE), pp. 36-43, 2002.Google Scholar
  18. 18.
    Mishra, P. and N. Dutt. Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. IFIP WCC Distributed and Parallel Embedded Systems (DIPES), pp. 81-90, 2002.Google Scholar
  19. 19.
    Mishra, P. et al. Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. Asia South Pacific Design Automation Conference (ASPDAC)/International Conference on VLSI Design, pp. 458-463, 2002.Google Scholar
  20. 20.
    Jhala, R. and K. L. McMillan. Microarchitecture Verification by Compositional Model Checking. Computer Aided Verification (CAV), pp. 396-410, 2001.Google Scholar
  21. 21.
    Leupers, R. and P. Marwedel. Retargetable Code Generation based on Structural Processor Descriptions. Design Automation for Embedded Systems, vol. 3,no. 1, 1998.Google Scholar
  22. 22.
    Hosabettu, R. M. Systematic Verification of Pipelined Microprocessors. Ph.D. Thesis. Department of Computer Science, University of Utah, 2000.Google Scholar
  23. 23.
    Symbolic Model Verifier, http://www.cs.cmu.edu/~modelcheck.Google Scholar
  24. 24.
    Trimaran Release: http://www.trimaran.org. The MDES User Manual, 1997.Google Scholar
  25. 25.
    Zivojnovic, V. et al. LISA—Machine Description Language and Generic Machine Model for HW/SW Co-Design. IEEE Workshop on VLSI Signal Processing, 1996.Google Scholar
  26. 26.
    Espresso, http://www-cad.eecs.berkeley.edu/Software/software.html.Google Scholar
  27. 27.
    Eqntott, http://www-ee.engr.ccny.cuny.edu/notes/ee210/eqntott_man.html.Google Scholar

Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • Prabhat Mishra
    • 1
  • Nikil Dutt
    • 1
  • Hiroyuki Tomiyama
    • 2
  1. 1.Center for Embedded Computer SystemsUniversity of CaliforniaIrvineUSA
  2. 2.Department of Information EngineeringNagoya University, Furo-choChikusa-ku, NagoyaJapan

Personalised recommendations