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Russian Microelectronics

, Volume 32, Issue 4, pp 243–246 | Cite as

Switch-Level Test-Vector Generation for CMOS Combinational Logic

  • A. E. Lyul'kin
Article

Abstract

A method is proposed of test-vector generation for stuck-open and other faults in CMOS combinational circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that should be applied to the element under test. (2) Trace a path through which the response could reach an output node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1) and (2). The method is illustrated with an example.

Keywords

Internal Node Output Node Logic Level Combinational Logic Combinational Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© MAIK Nauka/Interperiodica 2003

Authors and Affiliations

  • A. E. Lyul'kin
    • 1
  1. 1.Belarussian State UniversityMinskBelarus

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