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Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

  • Javier Ramírez
  • Antonio García
  • Uwe Meyer-Bäse
  • Fred Taylor
  • Antonio Lloris
Article

Abstract

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).

field-programmable logic residue number system distributed arithmetic discrete wavelet transform digital signal processing 

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Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • Javier Ramírez
    • 1
  • Antonio García
    • 1
  • Uwe Meyer-Bäse
    • 2
  • Fred Taylor
    • 3
  • Antonio Lloris
    • 1
  1. 1.Departamento de Electrónica y Tecnología de Computadores, Campus Universitario FuentenuevaUniversity of GranadaGranadaSpain
  2. 2.Department of Electrical and Computer EngineeringFAMU-FSU College of EngineeringTallahasseeUSA
  3. 3.High-Speed Digital Architecture Laboratory, Electrical and Computer Engineering, Computer and Information Science EngineeringUniversity of FloridaGainesvilleUSA

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