Evaluation of CORDIC Algorithms for FPGA Design

  • Javier Valls
  • Martin Kuhlmann
  • Keshab K. Parhi


This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.

CORDIC FPGA Two's complement redundant arithmetic 


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  1. 1.
    P.J. Graumann and L.E. Turner, “Implementing Digital Signal Processing Algorithms Using Pipelined Bit-Serial Arithmetic and Field Programmable Gate Arrays,” in First International ACM/SIGDA Workshop on Field Programmable Gate Arrays (FPGA'92), 1992.Google Scholar
  2. 2.
    J. Isoaho, J. Pasanen, O. Vainio, and H. Tenhunen, “DSP System Integration and Prototyping with FPGAs,” Journal of VLSI Signal Processing, vol. 6, 1993, pp. 155-172.CrossRefGoogle Scholar
  3. 3.
    M. Wahab and D. Puckey, “FPGA-Based DSP Systems,” in Abindon EE&CS books, W.R. Moore and W. Luk (Eds.), 1994.Google Scholar
  4. 4.
    R.J. Petersen and B. Hutchings, “An Assessment of the Suitability of FPGA-Based Systems for Use in DSPs,” in Lecture Notes in Computer Science, Springer-Verlag, Berlin, 1995, no. 975, pp. 293-302.Google Scholar
  5. 5.
    J.E. Volder, “The CORDIC Trigonometric Computing Technique,” IRE Trans. Electronic Computers, vol. EC-8,no. 3, 1959, pp. 330-334.CrossRefGoogle Scholar
  6. 6.
    J.S. Walther, “A Unified Algorithm for Elementary Functions,” in Proc. Spring. Joint Comput. Conference, vol. 38, 1971, pp. 379-385.Google Scholar
  7. 7.
    Y. Hu, “CORDIC-Based VLSI Architectures for Digital Signal Processing,” IEEE Signal Processing Magazine, vol. 9,no. 3, July 1992, pp. 16-35.CrossRefGoogle Scholar
  8. 8.
    R. Andraka, “A Survey of CORDIC Algorithms for FPGAs,” in Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA '98), Monterey, CA, Feb. 22–24, 1998, pp. 191-200.Google Scholar
  9. 9.
    U. Meyer-Base, A. Meyer-Base, and W. Hilberg, “COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA,” in 4th International Workshop on Field Programmable Logic and Applications (FPL'94), Prag, Czech Republic, 7–9 September, 1994.Google Scholar
  10. 10.
    C. Dick, “Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays,” in ACM/SIGDA Int. Symp. on Field Programmable Gate Array, Feb. 1996, pp. 129-135.Google Scholar
  11. 11.
    U. Meyer-Base, A. Meyer-Base, J. Mellott, and F. Taylor, “A Fast Modified CORDIC-Implementation of Radial Basis Neural Networks,” Journal of VLSI Signal Processing, vol. 20, 1998, pp. 211-218.CrossRefGoogle Scholar
  12. 12.
    M.A. Mayosky, P.E. Battaiotto, and G.M. Toccaceli, “A CORDIC Architecture for Vector Control,” in Proc. of the Int. Conf. on Signal Processing Applications and Technology, 1998.Google Scholar
  13. 13.
    N. Takagi, T. Asada, and S. Yajima, “Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation,” IEEE Transactions on Computers, vol. 40,no. 9, 1991.Google Scholar
  14. 14.
    J.-A. Lee and T. Lang, “Constant-Factor Redundant CORDIC for Angle Calculation and Rotation,” IEEE Transactions on Computers, vol. 41,no. 8, 1992.Google Scholar
  15. 15.
    H. Lin and A. Sips, “On-Line CORDIC Algorithms,” IEEE Transactions on Computers, vol. 39, 1990, pp. 1038-1052.CrossRefGoogle Scholar
  16. 16.
    J. Duprat and J.-M. Muller, “The CORDIC Algorithm: New Results for Fast VLSI Implementation,” IEEE Transactions on Computers, vol. 42, 1993, pp. 168-178.CrossRefGoogle Scholar
  17. 17.
    H. Dawid and H. Meyr, “The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations,” IEEE Transactions on Computers, vol. 45,no. 3, 1996.Google Scholar
  18. 18.
    S. Wang, V. Piuri, and E. Swartzlander, “Hybrid CORDIC Algorithms,” IEEE Transactions on Computers, vol. 46, 1997, pp. 1202-1207.CrossRefGoogle Scholar
  19. 19.
    C. Li and S. Chen, “A Radix-4 Redundant CORDIC Algorithm with Fast On-Line Variable Scale Factor Compensation,” in Int. Symposium of Circuit and Systems (ISCAS'97), Hong Kong, Jun. 1997, pp. 639-642.Google Scholar
  20. 20.
    R.R. Osorio, E. Antelo, J. Bruguera, and E. Zapata, “Digit On-Line Large Radix CORDIC Rotator,” in Int. Conf. On Application-Specific Array Processors, Strasbourg, France, Jul. 1995, pp. 247-257.Google Scholar
  21. 21.
    J. Villalba, J. Hidalgo, E. Zapata, E. Antelo, and J. Bruguera, “CORDIC Architectures with Parallel Compensation of the Scale Factor,” in Int. Conf. on Application-Specific Array Processors, Strabourg, France, Jul. 1995, pp. 258-269.Google Scholar
  22. 22.
    Shen-Fu Hsiao and Jean-Marc Delosme, “Householder CORDIC Algorithm,” IEEE Transactions on Computers, vol. 44,no. 8, 1995.Google Scholar
  23. 23.
    Shen-Fu Hsiao and Jen-Yin Chen, “Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure,” Journal of VLSI Signal Processing, vo. 20, 1998, pp. 267-278.Google Scholar
  24. 24.
    Shen-Fu, Hsiao, “A High-Speed Constant-Factor Redundant CORDIC Processor without Extra Correcting or Scaling Iterations,” in IEEE Int. Conf. On Circuits and Systems (ISCAS'99), Florida, 1999.Google Scholar
  25. 25.
    M. Kuhlmann and K.K. Parhi, “A High-Speed CORDIC Algorithm and Architecture for DPS Applications,” in Proc. of the 1999 IEEE Workshop on Signal Processing Systems (SiPS'99), Taipei, Taiwan, Oct. 1999.Google Scholar
  26. 26.
    M. Kuhlmann and K.K. Parhi, “A New CORDIC Rotation Method for Generalized Coodinate Systems,” in Proc. of the 1999 Asilomar Conference on Signal, Systems and Computers, Pacific Grove, CA, Oct. 1999.Google Scholar
  27. 27.
    J. Moran, I. Rios, and J. Meneses, “Signed Digit Arithmetic on FPGAs,” in More FPGAs, pp. 251-261, W.R. Moore and W. Luk (Eds.), Abindon EE&CS books, 1994.Google Scholar
  28. 28.
    K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley and Sons, 1999.Google Scholar
  29. 29.
    M.D. Ercegovac and T. Lang, “On-the-Fly Conversion of Redundant into Conventional Representations,” IEEE Transactions on Computers, vol. 36, 1987, pp. 895-897.CrossRefGoogle Scholar
  30. 30.
    D. Timmermann and S. Dolling, “Unfolded Redundant CORDIC VLSI Architectures with Reduced Area and Power Consumption,” in Int. Conf. on VLSI 97, Brasilia, Sept. 1997.Google Scholar
  31. 31.
    A. Wassatsch, S. Dolling, and D. Timmermann, “Area Minimization of Redundant CORDIC Pipeline Architectures,” in IEEE International Conference on Computer Design (ICCD '98), Austin, Texas, October 1998.Google Scholar

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Javier Valls
    • 1
  • Martin Kuhlmann
    • 2
  • Keshab K. Parhi
    • 2
  1. 1.Department of Ingenieria ElectronicaUniversidad Politecnica de ValenciaGrao de Gandia, ValenciaSpain
  2. 2.Broadcom CorporationIrvineUSA

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