Journal of Electronic Testing

, Volume 18, Issue 4–5, pp 475–485

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch

  • Subhayu Basu
  • Indranil Sengupta
  • Dipanwita Roy Chowdhury
  • Sudipta Bhawmik
Article

DOI: 10.1023/A:1016549725661

Cite this article as:
Basu, S., Sengupta, I., Roy Chowdhury, D. et al. Journal of Electronic Testing (2002) 18: 475. doi:10.1023/A:1016549725661

Abstract

The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches. An algorithm has been proposed for testing the cores using the TAM switch architecture. In addition, a scheme for testing the interconnections between cores in parallel is also presented. Experiments have been carried out on several synthetic SOC benchmarks. Results show significant optimization of area overhead as well as test time.

system-on-chip TAM switch interconnect testing 

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Subhayu Basu
    • 1
  • Indranil Sengupta
    • 2
  • Dipanwita Roy Chowdhury
    • 2
  • Sudipta Bhawmik
    • 3
  1. 1.Princeton UniversityUSA
  2. 2.Department of Computer Science and EngineeringIndian Institute of TechnologyKharagpurIndia
  3. 3.Agere SystemsHolmdelUSA

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