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A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation

  • Wael Badawy
  • Magdy Bayoumi
Article

Abstract

Affine transformation is widely used in image processing. Recently, it is recommended by MPEG-4 for video motion compensation. This paper presents a novel low power parallel architecture for texture warping using affine transformation (AT). The architecture uses a novel multiplication-free algorithm that employs the algebraic properties of the AT. Low power has been achieved at different levels of the design. At the algorithmic level, replacing multiplication operations with bit shifting saves the power and delay of using a multiplier. At the architecture level, low power is achieved by using parallel computational units, where the latency constraints and/or the operating latency can be reduced. At the circuit level, using low power building blocks (such as low power adders) contributes to the power savings. The proposed architecture is used as a computational kernel in video object coders. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 μm CMOS technology with three layers of metal. The performance of the proposed architecture shows that it can be used in mobile and handheld applications.

affine transformation texture mapping video object MPEG-4 low power VLSI 

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Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Wael Badawy
    • 1
  • Magdy Bayoumi
    • 2
  1. 1.Department of Electrical and Computer EngineeringUniversity of CalgaryCalgaryCanada
  2. 2.The Center for Advanced Computer StudiesUniversity of LouisianaLafayetteUSA

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