Journal of Electronic Testing

, Volume 18, Issue 3, pp 261–271 | Cite as

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits

  • P. Civera
  • L. Macchiarulo
  • M. Rebaudengo
  • M. Sonza Reorda
  • M. Violante


In this paper we describe an FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits. Suitable techniques are proposed, allowing emulating the effects of faults and observing faulty behavior. The proposed approach combines the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures can be achieved with respect to state-of-the-art simulation-based fault injection techniques.

fault injection FPGA-based fault emulation dependability evaluation fault tolerant circuits single event upset 


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Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • P. Civera
    • 1
  • L. Macchiarulo
    • 1
  • M. Rebaudengo
    • 2
  • M. Sonza Reorda
    • 2
  • M. Violante
    • 2
  1. 1.Dip. ElettronicaPolitecnico di TorinoTorinoItaly
  2. 2.Dip. Automatica e InformaticaPolitecnico di TorinoTorinoItaly

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