Journal of Electronic Testing

, Volume 18, Issue 2, pp 213–230

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

  • Vikram Iyengar
  • Krishnendu Chakrabarty
  • Erik Jan Marinissen
Article

DOI: 10.1023/A:1014916913577

Cite this article as:
Iyengar, V., Chakrabarty, K. & Marinissen, E.J. Journal of Electronic Testing (2002) 18: 213. doi:10.1023/A:1014916913577

Abstract

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.

Embedded core testing test access mechanism (TAM) test wrapper testing time integer linear programming 

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Vikram Iyengar
    • 1
  • Krishnendu Chakrabarty
    • 1
  • Erik Jan Marinissen
    • 2
  1. 1.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA
  2. 2.IC Design—Digital Design and TestPhilips Research LaboratoriesEindhovenThe Netherlands

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