The Journal of Supercomputing

, Volume 19, Issue 1, pp 57–75

Optimization of Dynamic Hardware Reconfigurations

  • Jürgen Teich
  • Sándor P. Fekete
  • Jörg Schepers
Article

Abstract

Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.

reconfigurable hardware multi-dimensional placement and packing 

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Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  • Jürgen Teich
    • 1
  • Sándor P. Fekete
    • 2
  • Jörg Schepers
    • 3
  1. 1.Computer EngineeringUniversity of PaderbornGermany
  2. 2.Department of MathematicsTU BerlinGermany
  3. 3.IBM GermanyKölnGermany

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