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The Journal of Supercomputing

, Volume 19, Issue 1, pp 7–22 | Cite as

Formally Analyzed Dynamic Synthesis of Hardware

  • Kong Woei Susanto
  • Tom Melham
Article

Abstract

Dynamic hardware reconfiguration based on run-time system specialization is viable with FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesis algorithm used to reconfigure FPGA designs at run-time. The verification approach is based on a deep embedding of a language for netlist and the relational hardware modeling style.

formal verification theorem proving partial evaluation FPGAs dynamic hardware reconfiguration 

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Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  • Kong Woei Susanto
    • 1
  • Tom Melham
    • 1
  1. 1.Department of Computing ScienceUniversity of GlasgowUkraine

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