Design Automation for Embedded Systems

, Volume 2, Issue 1, pp 33–60 | Cite as

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

  • Shuvra S. Bhattacharyya
  • Praveen K. Murthy
  • Edward A. Lee


Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations.

We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the trade-offs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.

Dataflow programming synchronous dataflow memory management multirate signal processing algorithms SDF compiler on-chip memory clustering minimum cuts dynamic programming 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    M. Ade, R. Lauwereins and A. Peperstraete. Buffer memory requirements in DSP applications. IEEE Wkshp. on Rapid System Prototyping, June 1994.Google Scholar
  2. 2.
    S. S. Bhattacharyya, P. K. Murthy and E. A. Lee. Two complementary heuristics for translating graphical DSP programs into minimum memory software implementations. Memorandum UCB/ERL M95/3, ElectronicsResearch Laboratory, University of California at Berkeley, Jan., 1995.Google Scholar
  3. 3.
    S. S. Bhattacharyya, P K. Murthy and E. A. Lee. Software Synthesis from Dataflow Graphs. Kluwer Academic Publishers, Norwell MA, 1996.Google Scholar
  4. 4.
    S. S. Bhattacharyya and E. A. Lee. Scheduling synchronous dataflow graphs for efficient looping. Jo. ofVLSI Signal Processing, Dec. 1993.Google Scholar
  5. 5.
    J. Buck, S. Ha, E. A. Lee and D. G. Messerschmitt. Ptolemy: a framework for simulating and prototyping heterogeneous systems. International Journal of Computer Simulation, Jan. 1995.Google Scholar
  6. 6.
    T. H. Cormen, C. E. Leiserson and R. L. Rivest. Introduction to Algorithms. McGraw-Hill, 1990.Google Scholar
  7. 7.
    J. Fabri. Automatic Storage Optimization. UMI Research Press, 1982.Google Scholar
  8. 8.
    M. R. Garey and D. S. Johnson. Computers and Intractability-A Guide to the Theory of NP-Completeness.Freeman, 1979.Google Scholar
  9. 9.
    R. Govindarajan, G. R. Gao and P. Desai. Minimizing memory requirements in rate-optimal schedules. Proc.of the Intl. Conf: on Application Specific Array Processors, San Francisco, Aug. 1994.Google Scholar
  10. 10.
    B. W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System TechnicaJournal, Feb. 1970.Google Scholar
  11. 11.
    R. Lauwereins, P. Wauters, M. Ade and J. A. Peperstraete. Geometric parallelism and cyclo-static dataflowin GRAPE-II. IEEE Wkshp. on Rapid System Prototyping, June 1994.Google Scholar
  12. 12.
    E. A. Lee, W. H. Ho, E. Goei, J. Bier and S. S. Bhattacharyya. Gabriel: A design environment for DSP.IEEE Trans. on Acoustics, Speech, and Signal Processing, Nov. 1989.Google Scholar
  13. 13.
    E. A. Lee, D. G. Messerschmitt. Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Trans. on Computers, Feb. 1987.Google Scholar
  14. 14.
    P. K. Murphy, S. S. Bhaaacharyya and E. A. Lee. "Joint Minimization of Code and Data for SynchronousDataflow Programs," Journal of Formal Methods in System Design, to appear in 1996.Google Scholar
  15. 15.
    D. R. O'Hallaron. The Assign Parallel Program Generator, Memorandum CMJ-CS-91-141, School of Computer Science, Carnegie Mellon University, May 1991.Google Scholar
  16. 16.
    J. Pino, S. Ha, E. A. Lee and J. T. Buck. Software synthesis for DSP using Ptolemy. Invited paper in Jo. of VLSI Signal Processing. Jan. 1995.Google Scholar
  17. 17.
    S. Ritz, S. Pankert, and H. Meyr. High level software synthesis for signal processing systems. Proc. of the Intl. Conf. on Application Specific Array Processors, Aug. 1992.Google Scholar
  18. 18.
    S. Ritz, M. Willems and II. Meyr. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. Proceedings of the ICASSP 95, Detroit, Michigan, May 1995.Google Scholar

Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Shuvra S. Bhattacharyya
    • 1
  • Praveen K. Murthy
    • 2
  • Edward A. Lee
    • 2
  1. 1.Semiconductor Research LaboratoryHitachi America, Ltd.San JoseUSA
  2. 2.Dept. of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

Personalised recommendations