Arithmetic Boolean Expression Manipulator Using BDDs
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Recently, there has been a lot of works on LSI design systems using Binary Decision Diagrams (BDDs), which are efficient representations of Boolean functions. We previously developed a Boolean expression manipulator, that can quickly calculate Boolean expressions by using BDD techniques. It has greatly assisted us in developing VLSI design systems and solving combinatorial problems.
In this paper, we present an Arithmetic Boolean Expression Manipulator (BEM-II), that is also based on BDD techniques. BEM-II calculates Boolean expressions that contain arithmetic operations, such as addition, subtraction, multiplication and comparison, and then displays the results in various formats. It can solve problems represented by a set of equalities and inequalities, which are dealt with in 0-1 linear programming. We discuss the algorithm and data structure used for manipulating arithmetic Boolean expressions and show the formats used for displaying the results.
The specifications for BEM-II are described and several application examples are presented. Arithmetic Boolean expressions will be useful for various applications. They perform well in terms of the total time for programming and execution. We expect BEM-II to facilitate research and development of digital systems.
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- 1.S. Akers, "Binary decision diagrams," IEEE Trans. Comput., Vol. C-27, No. 6, pp. 509-516, June 1978.Google Scholar
- 2.I. Bahar, E. Frohm, C. Gaona, G. Hachtel, W. Macil, A. Pardo, and F. Somenzi, "Algebraic decision diagrams and their applications," Proc. IEEE/ACM ICCAD'93, pp. 188-191, Nov. 1993.Google Scholar
- 3.K. Brace, R. Rudell, and R. Bryant, "Efficient implementation of a BDD package," ACM/IEEE Proc. 27th DAC, pp. 40-45, June 1990.Google Scholar
- 4.R. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., Vol. C-35, No. 8, pp. 677-691, Aug. 1986.Google Scholar
- 5.R. Bryant, "Symbolic Boolean manipulation with ordered binary decision diagrams," CMU CS Technical Report, No. CMU-CS-92-160, July 1992.Google Scholar
- 6.J. Burch, E. Clarke, K. McMillan, and D. Dill, "Sequential circuit verification using symbolic model checking," Proc. ACM/IEEE DAC'90, pp. 618-624, June 1992.Google Scholar
- 7.E. Clarke, K. McMillan, X. Zhao, M. Fujita, and J. Yang, "Spectral transforms for large Boolean functions with applications to technology mapping," Proc. ACM/IEEE DAC'93, pp. 54-60, June 1993.Google Scholar
- 8.M. Fujita, Y. Matsunaga, and T. Kakuda, "On variable ordering of binary decision diagrams for the application of multi-level logic synthesis," Proc. the European Conference on Design Automation, pp. 50-54, 1991.Google Scholar
- 9.G. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Probabilistic analysis of large finite state machines," Proc. ACM/IEEE DAC'94, pp. 270-275, June 1994.Google Scholar
- 10.S. Jeong and F. Somenzi, "A new algorithm for the binate covering problem and its application to the minimization of Boolean relations," Proc. IEEE ICCAD'92, pp. 417-420, Nov. 1992.Google Scholar
- 11.B. Lin and F. Somenzi, "Minimization of symbolic relations," Proc. IEEE ICCAD'90, pp. 88-91, Nov. 1990.Google Scholar
- 12.Y. Matsunaga and M. Fujita, "Multi-level logic optimization using binary decision diagrams," Proc. ICCAD'89, pp. 556-559, Nov. 1989.Google Scholar
- 13.S. Minato, "Minimum-width method of variable ordering for binary decision diagrams," IEICE Jpn. Trans. Fundamentals, Vol. E75-A, No. 3, pp. 392-399, March 1992.Google Scholar
- 14.S. Minato, "Fast generation of irredundant sum-of-products forms from binary decision diagrams," Proceedings of the Synthesis and Simulation Meeting and International Interchange.SASIMI'92, Japan/, pp. 64-73, March 1992.Google Scholar
- 15.S. Minato, N. Ishiura, and S. Yajima, "Fast tautology checking using shared binary decision diagram-benchmark results," Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pp. 580-584, Nov. 1989.Google Scholar
- 16.S. Minato, N. Ishiura, and S. Yajima, "Symbolic simulation using shared binary decision diagram," Record of 1989 IEICE National Convention, SA-7-5, pp. 1.206-1.207, Sept. 1989 (in Japanese).Google Scholar
- 17.T. Miyazaki, "Boolean-based formulation for data path synthesis," IEEE Asia-Pacific Conference on Circuits and Systems.APCCAS'92), pp. 201-205, Dec. 1992.Google Scholar
- 18.R. Rudell, "Dynamic variable ordering for ordered binary decision diagrams," Proc. IEEE/ACM ICCAD'93, pp. 42-47, Nov. 1993.Google Scholar
- 19.A. Takahara, "A timing analysis method for logic circuits," Record of 1993 IEICE National Convention, A-120, pp. 1-120, March 1993 (in Japanese).Google Scholar