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Journal of Electronic Testing

, Volume 13, Issue 2, pp 79–91 | Cite as

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

  • Sujit Dey
  • Anand Raghunathan
  • Kenneth D. Wagner
Article

Abstract

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.

behavioral synthesis for testability behavioral synthesis for BIST design for testability high-level test generation RTL synthesis for testability 

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Copyright information

© Kluwer Academic Publishers 1998

Authors and Affiliations

  • Sujit Dey
    • 1
  • Anand Raghunathan
    • 2
  • Kenneth D. Wagner
    • 3
  1. 1.Department of ECEUniversity of CaliforniaSan Diego, La Jolla
  2. 2.C&C Research LabsNEC USAPrinceton
  3. 3.Siemens Microelectronics IncSan Jose

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