Journal of Electronic Testing

, Volume 15, Issue 1–2, pp 63–73 | Cite as

New Techniques for Deterministic Test Pattern Generation

  • Ilker Hamzaoglu
  • Janak H. Patel

Abstract

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time.

automatic test generation stuck-at fault redundancy scan design logic implications Boolean satisfiability 

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References

  1. 1.
    P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,” IEEE Trans. on Computers, pp. 21–222, March 1981.Google Scholar
  2. 2.
    H. Fujiwara and S. Toida, “The Complexity of Fault Detection Problems for Combinational Logic Circuits,” IEEE Trans. on Computers, pp. 555–560, June 1982.Google Scholar
  3. 3.
    M. Abramovici, J.J. Kulikowski, P.R. Menon, and D.T. Miller, “SMART and FAST:Test Generation for VLSI Scan-Design Circuits,” IEEE Design & Test of Computers, pp. 43–54, Aug. 1986.Google Scholar
  4. 4.
    H. Fujiwara and T. Shimono, “On the Acceleration of Test Generation Algorithms,” IEEE Trans. on Computers, pp. 1137–1144, Dec. 1983.Google Scholar
  5. 5.
    T. Kirkland and M.R. Mercer, “A Topological Search Algorithm for ATPG,” Proc. of the Design Automation Conf., June 1987, pp. 502–508.Google Scholar
  6. 6.
    W. Kunz and D. Pradhan, “Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits,” Proc. of the Int. Test Conf., Sept. 1992, pp. 816–825.Google Scholar
  7. 7.
    M.H. Schulz, E. Trischler, and T.M. Sarfert, “SOCRATES: A Highly Efficient Automatic Test Pattern Generation System,” IEEE Trans. on Computer-Aided Design, pp. 126–137, Jan. 1988.Google Scholar
  8. 8.
    M.H. Schulz and E. Auth, “Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification,” IEEE Trans. on Computer-Aided Design, pp. 811–816, July 1989.Google Scholar
  9. 9.
    J.P.M. Silva and K.A. Sakallah, “Dynamic Search-Space Pruning Techniques in Path Sensitization,” Proc. of the Design Automation Conf., June 1994, pp. 705–711.Google Scholar
  10. 10.
    J.A. Waicukauski, P.A. Shupe, D.J. Giramma, and A. Matin, “ATPG for Ultra-Large Structured Designs,” Proc. of the Int. Test Conf., Aug. 1990, pp. 44–51.Google Scholar
  11. 11.
    S.T. Chakradhar, V.D. Agrawal, and S.G. Rothweiler, “A Transitive Closure Algorithm for Test Generation,” IEEE Trans. on Computer-Aided Design, pp. 1015–1028, July 1993.Google Scholar
  12. 12.
    T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Trans. on Computer-Aided Design, pp. 4–15, Jan. 1992.Google Scholar
  13. 13.
    J.P.M. Silva and K.A. Sakallah, “Robust Search Algorithms for Test Pattern Generation,” Proc. of the Fault-Tolerant Computing Symp., June 1997, pp. 152–161.Google Scholar
  14. 14.
    P. Stephan, R.K. Brayton and A.L. Sagiovanni-Vincentelli, “Combinational Test Generation Using Satisfiability,” IEEE Trans. on Computer-Aided Design, pp. 1167–1176, Sept. 1996.Google Scholar
  15. 15.
    F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran,” Proc. of the Int. Symp. on Circuits and Systems, June 1985.Google Scholar
  16. 16.
    F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Proc. of the Int. Symp. on Circuits and Systems, May 1989, pp. 1929–1934.Google Scholar
  17. 17.
    T.M. Niermann, W. Cheng, and J.H. Patel, “PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator,” IEEE Trans. on Computer-Aided Design, pp. 198–207, Feb. 1992.Google Scholar
  18. 18.
    S.J. Chandra and J.H. Patel, “Experimental Evaluation of Testability Measures for Test Generation,” IEEE Trans. on Computer-Aided Design, pp. 93–97, Jan. 1989.Google Scholar
  19. 19.
    L.H. Goldstein and E.L. Thigpen, “SCOAP: Sandia Controllability/Observability Analysis Program,” Proc. of the Design Automation Conf., 1980, pp. 190–196.Google Scholar
  20. 20.
    S. Kundu, L.M. Huisman, I. Nair, V. Iyengar, and L.N. Reddy, “A Small Test Generator for Large Designs,” Proc. of the Int. Test Conf., Sept. 1992, pp. 30–40.Google Scholar
  21. 21.
    R.P. Kunda, P. Narain, J.A. Abraham, and B.D. Rathi, “Speed Up of Test Generation Using High-Level Primitives,” Proc. of the Design Automation Conf., June 1990, pp. 594–599.Google Scholar
  22. 22.
    Y. Matsunaga and M. Fujita, “A Fast Test Pattern Generator for Large Scale Circuits,” Proc. of the Synth. Simulation Meeting Int. Interchange, April 1992, pp. 263–271.Google Scholar
  23. 23.
    K.T. Cheng, “Gate-Level Test Generation for Sequential Circuits,” ACM Trans. on Design Automation, pp. 405–442, Oct. 1996.Google Scholar
  24. 24.
    T.M. Niermann and J.H. Patel, “HITEC:A Test Generation Package for Sequential Circuits,” Proc. of the European Design Automation Conf., Feb. 1991, pp. 214–218.Google Scholar

Copyright information

© Kluwer Academic Publishers 1999

Authors and Affiliations

  • Ilker Hamzaoglu
    • 1
  • Janak H. Patel
    • 1
  1. 1.enter for Reliable & High-Performance ComputingUniversity of IllinoisUrbanaUSA

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