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Journal of Electronic Testing

, Volume 13, Issue 1, pp 29–40 | Cite as

On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

  • Sebastian Fenn
  • Michael Gossel
  • Mohammed Benaissa
  • David Taylor
Article

Abstract

In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m these overheads are particularly low. The fault coverage of the presented structures has been investigated by simulation experiment and shown to range between 90% and 94.3%.

finite fields multipliers parity checking on-line error detection 

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Copyright information

© Kluwer Academic Publishers 1998

Authors and Affiliations

  • Sebastian Fenn
    • 1
  • Michael Gossel
    • 2
  • Mohammed Benaissa
    • 3
  • David Taylor
    • 3
  1. 1.Department of Electronic and Electrical EngineeringThe University of HuddersfieldQueensgate, Huddersfield, West YorkshireUK
  2. 2.Fault Tolerant Computing GroupThe University of PotsdamPotsdamGermany
  3. 3.Department of Electronic and Electrical EngineeringThe University of HuddersfieldQueensgate, Huddersfield, West YorkshireUK

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