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Journal of Electronic Testing

, Volume 16, Issue 5, pp 487–498 | Cite as

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

  • Said Hamdioui
  • Ad J. Van De Goor
Article
  • 61 Downloads

Abstract

A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced. In addition, the consequences of the port restrictions (read-only or write-only ports) on the fault models and tests are discussed, together with the test strategy.

multi-port memories single-port memories fault models address decoder faults march tests fault coverage read-only ports write-only ports 

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Copyright information

© Kluwer Academic Publishers 2000

Authors and Affiliations

  • Said Hamdioui
  • Ad J. Van De Goor

There are no affiliations available

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