Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy
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A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced. In addition, the consequences of the port restrictions (read-only or write-only ports) on the fault models and tests are discussed, together with the test strategy.
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- 1.M.J. Raposa, “Dual Port Static RAM Testing,” Proc. IEEE International Test Conference, 1988, pp. 362-368.Google Scholar
- 2.B. Nadeau-Dostie, A. Sulburt, and V.K. Agrawal, “Serial Interfacing for Embedded-memory Testing,” IEEE Design and Test of Computers, Vol. 7, No. 2, pp. 52-63, 1990.Google Scholar
- 3.V.C. Alves and M. Nicolaidis, “Detecting Complex Coupling Fault in Multi-Port RAMs,” IMAG Research Report No. RR978, Feb. 1991.Google Scholar
- 4.M. Nicolaidis, V.C. Alves, and H. Bederr, “Testing Complex Couplings in Multi-Port Memories,” IEEE Transactions on VLSI Systems, Vol. 3, No. 1, pp. 59-71, March 1995.Google Scholar
- 5.S. Hamdioui, “Fault Models andTests for Multi-Port Memories,” Technical Report No. 168340-28(1997)-11, Delft University of Technology, Faculty of Information Technology and Systems, Delft, The Netherlands, Oct. 1997.Google Scholar
- 6.A.J. van de Goor and S. Hamdioui, “Fault Models and Tests for Two-Port Memories,” 16th IEEE VLSI Test Symposium, April 1998, pp. 401-410.Google Scholar
- 7.S. Hamdioui and A.J. van de Goor, “Consequence of Port Restrictions on Testing Two-Port Memories,” International Test Conference ITC'98, Washington, USA, Oct. 1998, pp. 63-72.Google Scholar
- 8.S. Hamdioui and A.J. van de Goor, “Address Decoder Faults and their Tests in Two-Port Memories,” Memory Technology, Design and Testing, San Jose, California, USA, Aug. 1998, pp. 97-103.Google Scholar
- 9.S. Hamdioui and A.J. van de Goor, “Consequence of Port Restrictions on Testing Address Decoder Faults in Two-Port Memories,” Seventh Asian Test Symposium, Singapore, Dec. 1998, pp. 340-347.Google Scholar
- 10.A.J. van de Goor, Testing Semiconductors Memories, Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998. E-mail: vdGoor@cardit.et.tudelft.nlGoogle Scholar
- 11.M. Renovell, P. Huc, and Y. Bertrand, “Bridging Faults Coverage Improvement by Power Supply Control,” 14th IEEE VLSI Test Symposium, 1996, pp. 338-343.Google Scholar