Journal of Electronic Testing

, Volume 13, Issue 2, pp 105–120 | Cite as

RTL Test Justification and Propagation Analysis for Modular Designs

  • Yiorgos Makris
  • Alex Orailogcaron;lu


Modular decomposition and functional abstraction are commonly employed to accommodate the growing size and complexity of modern designs. In the test domain, a divide-and-conquer type of approach is utilized, wherein test is locally generated for each module and consequently translated to global design test. We present an RTL analysis methodology that identifies the test justification and propagation bottlenecks, facilitating a judicious DFT insertion process. We introduce two mechanisms for capturing, without reasoning on the complete functional space, data and control module behavior related to test translation. A traversal algorithm that identifies the test translation bottlenecks in the design is described. The algorithm is capable of handling cyclic behavior, reconvergence and variable bit-widths in an efficient manner. We demonstrate our scheme on representative examples, unveiling its potential of accurately identifying and consequently minimizing the reported controllability and observability bottlenecks of large, modular designs.

RTL testability analysis test justification test propagation modular design DFT 


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  1. 1.
    C-H. Chen, T. Karnik, and D.G. Saab, “Structural and Behavioral Synthesis for Testability Techniques,” IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 13, No. 6, pp. 777–785, June 1994.Google Scholar
  2. 2.
    I. Ghosh, A. Raghunathan, and N.K. Jha, “A Design for Testability Technique for RTL Circuits using Control/Data Flow Extraction,” Proc. IEEE/ACM International Conference on Computer Aided Design, 1996, pp. 329–336.Google Scholar
  3. 3.
    I. Ghosh, N. Jha, and S. Dey, “A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems,” Proc. International Test Conference, 1997, pp. 50–59.Google Scholar
  4. 4.
    A. Orailoğlu and I. Harris, “Microarchitectural Synthesis for Rapid BIST Testing,” IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 6, No. 6, pp. 573–586, June 1997.Google Scholar
  5. 5.
    B. Pouya and N. Touba, “Modifying User-Defined Logic for Test Access to Embedded Cores,” Proc. International Test Conference, 1997, pp. 60–68.Google Scholar
  6. 6.
    R.S. Tupuri and J.A. Abraham, “A Novel Test Generation Method for Processors using Commercial ATPG,” Proc. International Test Conference, 1997, pp. 743–752.Google Scholar
  7. 7.
    P. Vishakantaiah, T. Thomas, J.A. Abraham, and M.S. Abadir, “AMBIANT: Automatic Generation of Behavioral Modifications for Testability,” Proc. IEEE International Conference on Computer Design, 1993, pp. 63–66.Google Scholar
  8. 8.
    F. Corno, P. Prinetto, and M. Sonza Reorda, “Testability Analysis and ATPG on Behavioral RT-Level VHDL,” Proc. International Test Conference, 1997, pp. 753–759.Google Scholar
  9. 9.
    J. Lee and J. Patel, “Testability Analysis Based on Structural and Behavioral Information,” Proc. 11th IEEE VLSI Test Symposium, 1993, pp. 139–145.Google Scholar
  10. 10.
    P. Vishakantaiah, J.A. Abraham, and M.S. Abadir, “Automatic Test Knowledge Extraction from VHDL (ATKET),” Proc. 29th ACM/IEEE Design Automation Conference, 1992, pp. 273–278.Google Scholar
  11. 11.
    B.T. Murray and J.P. Hayes, “Test Propagation Through Modules and Circuits,” Proc. International Test Conference, 1991, pp. 748–757.Google Scholar
  12. 12.
    M.C. Hansen and J.P. Hayes, “High-Level Test Generation Using Symbolic Scheduling,” Proc. International Test Conference, 1995, pp. 586–595.Google Scholar
  13. 13.
    K.T. Cheng and A.S. Krishnakumar, “Automatic Functional Test Generation using the Extended Finite State Machine Model,” Proc. 30th ACM/IEEE Design Automation Conference, 1992, pp. 86–91.Google Scholar
  14. 14.
    D. Moundanos, J.A. Abraham, and Y.V. Hoskote, “A Unified Framework for Design Validation and Manufacturing Test,” Proc. International Test Conference, 1996, pp. 875–884.Google Scholar
  15. 15.
    J.P. Hayes, Computer Architecture and Organization, 3rd edition, McGraw-Hill, 1998.Google Scholar
  16. 16.
    P. Ashenden, The Designer's Guide to VHDL, 1st edition, Morgan-Kaufmann Publishers Inc., 1996.Google Scholar
  17. 17.
    T. Niermann and J. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Conference on Design Automation, 1992, pp. 214–218.Google Scholar
  18. 18.
    T. Niermann, W.T. Cheng, and J. Patel, “PROOFS: A Fast, Memory Efficient Sequential Circuit Fault Simulator,” Proc. 27th ACM/IEEE Design Automation Conference, 1990, pp. 535–540.Google Scholar

Copyright information

© Kluwer Academic Publishers 1998

Authors and Affiliations

  • Yiorgos Makris
    • 1
  • Alex Orailogcaron;lu
    • 1
  1. 1.CSE DepartmentReliable Systems Synthesis LabLa Jolla

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