# Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

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## Abstract

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.

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## References

- 1.T. Kohonen,
*Content-Addressable Memories*, 2 edition. Springer Verlag, Berlin, 1987.Google Scholar - 2.T. Kohonen,
*Self-Organization and Associative Memory*, 2 edition. Springer Verlag: Berlin, 1988.Google Scholar - 4.M. R. Emerling M. A. Sivilotti and C. A. Mead, VLSI architectures for implementation of neural networks. In (J. J. Denker, ed.),
*Neural Networks for Computing*. AIP: Snowbird UT, 1986, pages 408–413Google Scholar - 5.K. A. Boahen and A. G. Andreou, “Design of a bidirectional associative memory chip,” in
*Associative Neural Memories: Theory and Implementation*(M. Hassoun, ed.), chapter 17. Oxford University Press: New York, NY, 1993.Google Scholar - 6.P. O. Pouliquen, A. G. Andreou, K. Strohbehn, and R. E. Jenkins, “An associative memory integrated system for character recognition,” in
*Proc. 36th Midwest Symp. on Circuits and Systems*, Detroit, MI, Aug. 1993, pp. 762–765.Google Scholar - 7.Y. He, U. Cilingiroglu, and E. Sánchez-Sinencio, “A high density and low-power charge-based hamming network.”
*IEEE Trans. VLSI Systems*1(1), pp. 55–62, March 1993.Google Scholar - 8.Y. Horio and S. Nakamura, “Analog memories for VLSI neurocomputing,” in
*Artificial Neural Networks: Paradigms, Applications, and Hardware Implementations*(E. Sánchez-Sinencio and C. Lau, eds.), IEEE Press, Piscataway, NJ, 1992, pp. 344–366.Google Scholar - 9.G. Cauwenberghs, C. F. Neugebauer, and A. Yariv, “Analysis and verification of an analog VLSI incremental outer-product learning systems.”
*IEEE Trans. Neural Networks*3(3), May 1992.Google Scholar - 10.H. Yang, B. J. Sheu, and J.-C. Lee, “A nonvolatile analog neural memory using floating-gate MOS transistors.”
*Analog Integrated Circuits and Signal Processing*2(1), Feb. 1992.Google Scholar - 11.K. A. Boahen, P. O. Pouliquen, A. G. Andreou, and R. E. Jenkins, “A heteroassociative memory using current-mode MOS analog VLSI circuits.”
*IEEE Trans. Circuits and Systems*CAS-36(5), pp. 747–755, May 1989.Google Scholar - 12.K. A. Boahen, A. G. Andreou, and P. O. Pouliquen, “Architectures for associative memories using current-mode analog MOS circuits,” in
*Advanced Research in VLSI: Proc. Dec. Caltech Conference on VLSI*(C. L. Seitz, ed.). MIT Press: Cambridge, MA, 1989.Google Scholar - 13.Eric Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation.”
*IEEE J. Solid-State Circ.*12, pp. 224–231, 1977.Google Scholar - 14.C. A. Mead,
*Analog VLSI and Neural Systems*. Addison-Wesley: Reading, MA, 1989.Google Scholar - 15.A. G. Andreou and K. A. Boahen, “Neural information processing II,” in
*Analog VLSI Signal and Information Processing*(M. Ismael and T. Fiez, eds.). McGraw-Hill, 1994.Google Scholar - 16.K. Seno, K. Knorpp, L.-L. Shu, N. Teshima, H. Kihari, H. Sato, F. Miyaji, M. Takeda, M. Sasaki, Y. Tomo, P. T. Chuang, and K. Kobayashi, “A 9-ns 16-mb CMOS SRAM with offset-compensated current sense amplifier.”
*IEEE J. Solid-State Cicuits*28(11), pp. 1119–1124, November 1993.Google Scholar - 17.K. Sasaki, K. Ueda, K. Takasugi, H. Toyoshima, K. Ishibashi, T. Yamanaka, N. Hashimoto, and N. Ohki, “A 16-mb CMOS SRAM with a 2.3-μ
*m*^{2}single bit line memory cell.”*IEEE J. Solid-State Cicuits*28(11), pp. 1125–1130, November 1993.Google Scholar - 18.R. F. Lyon and R. R. Schediwy, “CMOS static memory with a new four-transistor memory cell,” in
*Advanced Research in VLSI*(P. Losleben, ed.). MIT Press: Cambridge, MA, 1987, pp. 110–132Google Scholar - 19.G. A. Carpenter and S. Grossberg, “A massively parallel architecture for a self-organizing neural pattern recognition machine.”
*Computer Vision, Graphics, and Image Processing*37, pp. 54–115, 1987.Google Scholar - 20.J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. Mead, “Winner-take-all networks of o(n) complexity,” in
*Advances in Neural Information Processing Systems 1*(D. Touretzky, ed.). Morgan Kaufmann: San Manteo, CA, 1989, pp. 703–711Google Scholar - 21.B. Gilbert, “Translinear circuits: A proposed classification.”
*Electronics Letters*11(1), pp. 14–16, 136, January 9, 1975.Google Scholar - 22.A. G. Andreou and K. A. Boahen, “Translinear circuits in subthreshold mos.”
*J. Analog Integrated Circ. Sig. Proc.*9, pp. 141–166, 1996.Google Scholar - 23.A. Pavasović, A. G. Andreou, and C. R. Westgate, “Characterization of subthreshold MOS mismatch in transistors for VLSI systems.”
*Journal of Analog Integrated Circuits and Signal Processing*6, pp. 75–85, July 1994.Google Scholar - 24.N. Kumar, P. O. Pouliquen, and A. G. Andreou, “Device mismatch limitations on the performance of an associative memory system,” in
*Proc. 36th Midwest Symp. on Circuits and Systems*(IEEE, ed.), 1993, pp. 570–573.Google Scholar - 25.H. Miwa, N. Kumar, P. O. Pouliquen, and A. G. Andreou, “Memory enhancement techniques for mixed digital memory-analog computational engines,” in
*Proc. IEEE Int. Symp. on Circuits and Systems*, volume 5, June 1994, pp. 45–48.Google Scholar