Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic

  • Uwe Meyer-Bäse
  • Antonio García
  • Fred Taylor
Article

Abstract

Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of revolutionizing sectors of digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPGAs were considered to be only a rapid prototyping and low-volume production technology. FPGAs are now attempting to move into the mainstream DSP as their density and performance envelope steadily improve. While evidence now supports the claim that FPGAs can accelerate selected low-end DSP applications (e.g., FIR filter), the technology remains limited in its ability to realize high-end DSP solutions. This is due primarily to systemic weaknesses in FPGA-facilitated arithmetic processing. It will be shown that in such cases, the residue number system (RNS) can become an enabling technology for realizing embedded high-end FPGA-centric DSP solutions. This thesis is developed in the context of a demonstrated RNS/FPGA synergy and the application of the new technology to communication signal processing.

field-programmable logic (FPL) field programmable gate array (FPGA) complex programmable logic devices (CPLD) digital signal processing (DSP) residue number system (RNS) channelizer zero-IF filter 

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Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  • Uwe Meyer-Bäse
    • 1
  • Antonio García
    • 2
  • Fred Taylor
    • 3
  1. 1.Department of Electrical and Computer EngineeringFAMU-FSU College of EngineeringTallahasser
  2. 2.Dpto. Ingeniería Inform´ticaUniversidad Autónoma de MadridUSA
  3. 3.High Speed Digital Architecture LaboratoryUniversity of FloridaGainesville

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