Linear QR Architecture for a Single Chip Adaptive Beamformer

  • G. Lightbody
  • R. Walke
  • R. Woods
  • J. McCanny
Article

Abstract

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

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Copyright information

© Kluwer Academic Publishers 2000

Authors and Affiliations

  • G. Lightbody
    • 1
  • R. Walke
    • 2
  • R. Woods
    • 3
  • J. McCanny
    • 1
  1. 1.DSiP™ LaboratoriesQueen's University of BelfastBelfastN. Ireland
  2. 2.DERAMalvernEngland
  3. 3.Hardware Systems GroupQueen's University of BelfastBelfastN. Ireland

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