Abstract
In this paper, a serial architecture for acceleration and implementation of Decision Tree (DT) training algorithm has been proposed. This architecture is compatible with 32-bit integer as well as fixed-point training data. In the worst case scenario, the FPGA implementation of the proposed architecture for Two Means DT (TMDT) algorithm is proved to run at least \(28\times \) faster than conventional C4.5 training algorithm widely used in many machine learning classifications. The proposed architecture is implemented on FPGA platform operating at maximum frequency of 62 MHz. Further, the hardware implementation is proved to run at least \(10\times \) faster than the software implementation in worst condition. This design has been tested on five binary datasets of variable size and dimension. Thus, the proposed hardware realisation is compatible to wide range of training datasets.
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This article is part of the topical collection “Hardware for AI, Machine Learning and Emerging Electronic Systems” guest edited by Himanshu Thapliyal, Saraju Mohanty and VS Kanchana Bhaaskaran.
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Choudhury, R., Ahamed, S.R. & Guha, P. Efficient Hardware Implementation of Decision Tree Training Accelerator. SN COMPUT. SCI. 2, 360 (2021). https://doi.org/10.1007/s42979-021-00748-9
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DOI: https://doi.org/10.1007/s42979-021-00748-9