Abstract
In this paper, we present a novel cylindrical gate-all-around heterostructure TFET that benefits from recessed gate architecture to enable line tunneling of charge carriers normal to the gate at InGaAs/InP heterojunction. In the proposed TFET, the channel and drain regions are composed of a wide-bandgap semiconductor which results in a considerable suppression of ambipolar conduction and off-state current. The device characteristics are investigated by numerical simulations and the results indicate impressive switching performance of the proposed transistor. Owing to designed geometry and employed material system, we obtain an extremely steep subthreshold swing, sub 3mv/dec over 6 decades of drain current, sub 60mv/dec over 10 decades of drain current, and average subthreshold swing of 21mv/dec, an on-state to off-state current ratio of about 1012, and an on-state current of about 100nA at VGS = 0.3 V. The influence of variations in the device dimensions, doping and bias condition on its electrical characteristics is also studied and discussed physically.
Similar content being viewed by others
References
G. Dewey, B. Chu-Kung, J. Boardman et al., Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing, in Technical Digest - International Electron Devices Meeting, IEDM (2011), pp. 785–788
V. Brouzet, B. Salem, P. Periwal et al., Fabrication and electrical characterization of homo- and hetero-structure Si/SiGe nanowire tunnel field effect transistor grown by vapor–liquid–solid mechanism. Solid-State Electron. 118, 26–29 (2016)
T. Vasen, P. Ramvall, A. Afzalian et al., Vertical gate-all-around nanowire GaSb-InAs core-shell n-type tunnel FETs. Sci. Rep. 9(1), 202 (2019)
J. Yoon, K. Kim, C. Baek, Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors. Sci. Rep. 23(7), 1–9 (2017)
D. Keighobadi, S. Mohammadi, Physical and analytical modeling of drain current of double-gate heterostructure tunnel FETs. Semicond. Sci. Technol. 34, 1–13 (2018)
A.N. Hanna, H.M. Fahad, M.M. Hussain, InAs/Si hetero-junction nanotube tunnel transistors. Sci. Rep. 5, 9843 (2015)
Z. Yang, Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett. 37(7), 839–842 (2016)
S.W. Kim, J.H. Kim, T.K. Liu, W.Y. Choi, B. Park, Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans. Electron Devices 63(4), 1774–1778 (2016)
S. Agarwal, J.T. Teherani, J.L. Hoyt, D.A. Antoniadis, E. Yablonovitch, Engineering the electron–hole bilayer tunneling field-effect transistor. IEEE Trans. Electron Devices 61(5), 1599–1606 (2014)
J.L. Padilla, C. Medina-Bailon, C. Alper, F. Gamiz, A.M. Ionescu, Confinement-induced InAs/GaSb heterojunction electron–hole bilayer tunneling field-effect transistor. Appl. Phys. Lett. 112(18), 182101 (2018)
P.-C. Shih, W.-C. Hou, J.-Y. Li, A U-gate InGaAs/GaAsSb Heterojunction TFET of tunneling normal to the gate with separate control over on- and off-state current. IEEE Electron Device Lett. 38(12), 1751–1754 (2017)
W. Wang, P. Wang, C. Zhang et al., Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices 61(1), 193–197 (2014)
S. Chen, S. Wang, H. Liu, W. Li, Q. Wang, X. Wang, Symmetric U-shaped gate tunnel field-effect transistor. IEEE Trans. Electron Devices 64(3), 1343–1349 (2017)
G. Musalgaonkar, S. Sahay, R.S. Saxena, M.J. Kumar, A line tunneling field-effect transistor based on misaligned core–shell gate architecture in emerging nanotube FETs. IEEE Trans. Electron Devices 66(6), 2809–2816 (2019)
A. Goel, S. Rewari, S. Verma, R.S. Gupta, Temperature-dependent gate-induced drain leakages assessment of dual-metal nanowire field-effect transistor—analytical model. IEEE Trans. Electron Devices 66, 2437–2445 (2019)
A. Goel, S. Rewari, S. Verma, R.S. Gupta, Novel dual-metal junctionless nanotube field-effect transistors for improved analog and low-noise applications. J. Electron. Mater. 50, 108–119 (2021)
A. Goel, S. Rewari, S. Verma, R.S. Gupta, High-K spacer dual-metal gate stack underlap junctionless gate all around (HK-DMGS-JGAA) MOSFET for high frequency applications. Microsyst. Technol. 26, 1697–1705 (2020)
A. Goel, S. Rewari, S. Verma, R.S. Gupta, Shallow extension engineered dual material surrounding gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance. AEU Int. J. Electron. Commun. 111, 152924 (2019)
SOFTWARE, D.S.: Device Simulator Atlas: Atlas User’s Manual (Silvaco, Inc, 2016)
H.R.T. Khaveh, S. Mohammadi, Potential and drain current modeling of gate-all-around tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans. Electron Devices 63(12), 5021–5029 (2016)
D. Keighobadi, S. Mohammadi, M. Fathipour, An analytical drain current model for the cylindrical channel gate-all-around heterojunction tunnel FETs. IEEE Trans. Electron Devices 66(8), 3646–3651 (2019)
R.N. Sajjad, W. Chern, J.L. Hoyt, D.A. Antoniadis, Trap assisted tunneling and its effect on subthreshold swing of tunnel field effect transistors. IEEE Trans. Electron Devices 63(11), 4380–4387 (2016)
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Keighobadi, D., Mohammadi, S. & Mohtaram, M. Recessed Gate Cylindrical Heterostructure TFET, a Device with Extremely Steep Subthreshold Swing. Trans. Electr. Electron. Mater. 23, 81–87 (2022). https://doi.org/10.1007/s42341-021-00321-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s42341-021-00321-4