## Abstract

In this paper, we have discussed threshold voltage and drain induced barrier lowering in NCFET. Threshold voltage in NCFET is lower as compared to MOSFET which is mainly because of negative equivalent oxide capacitance in NCFET. Further, we have discussed drain induced barrier lowering in NCFET and MOSFET. An increase in drain bias in MOSFET leads to decrease in threshold voltage and an increase in leakage current whereas in NCFET increase in drain bias leads to increase in threshold voltage and decrease in leakage current. We have obtained a positive value of DIBL factor for MOSFET and negative value for NCFET.

## Introduction

Ever-increasing demand for ultra-low power and high performance circuits has forced the semiconductor industry to continue the trend of downscaling in MOSFETs. However, below 100 nm technology node, short channel effects and power dissipation has become a cause of concern. Short channel effects mainly arise because of poor control of gate over the channel hence can be countered with FinFETs [1]. Dynamic power dissipation can be countered by scaling the supply voltage; however reducing supply voltage deteriorates the speed of device significantly. Now to maintain the same transistor speed threshold voltage needs to be reduced, which exponentially increases the leakage current and hence static power dissipation [2]. Hence it looks impossible to maintain a balance between performance and power dissipation. One possible way to maintain a balance between both the contradicting requirements is to reduce subthreshold swing of the device. Subthreshold swing is defined as gate voltage required to change the current by 1 decade.

However subthreshold swing for conventional MOSFET is limited to Boltzmann tranny [3] i.e. SS of MOSFET can have a minimum value of 60 mV per decade which means lowering the gate voltage below threshold voltage increases the leakage current by 10 times. Expression for the subthreshold swing of MOSFET is given by:

Subthreshold swing of MOSFET cannot be reduced below 60 mV per decade because body factor of MOSFET \(\left( {1 + C_{dep} /C_{ox} } \right)\) is always greater than unity. Hence the minimum value of subthreshold swing is 60 mV per decade which can be obtained if oxide capacitance is infinite. One way to reduce SS below 60 mV per decade is to make oxide capacitance negative in nature. This can be possible if ferroelectric material is used, which inherits the property of negative capacitance [4,5,6,7]. In NCFET, equivalent oxide capacitance \(\left( {C_{ox }^{'} } \right)\) is series combination of dielectric \(\left( {C_{ox} } \right)\) and ferroelectric capacitance \(\left( {C_{F} } \right)\).

Hence subthreshold swing for NCFET can be expressed as:

Subthreshold swing can be reduced below 60 mV per decade [8,9,10] if equivalent oxide capacitance \(\left( {C_{ox }^{'} } \right)\) is negative which is only possible if \(C_{ox} > \left| {C_{F} } \right|\). Ensuring the mentioned condition SS can be reduced below the Boltzmann limit. Negative value of equivalent oxide capacitance is also responsible for reduction of threshold voltage in NCFET which has been discussed in the further sections. Further, we have discussed drain induced barrier lowering (which is responsible for variation in threshold voltage) in MOSFET and NCFET. DIBL factor is positive for MOSFET and negative for NCFET which is because of drain induced barrier rising (reverse DIBL) [11, 12] in NCFET. Other than negative DIBL, NDR in drain characteristics of NCFET is also a unique feature that is observed in NCFET [13,14,15,16].

## Basics of NCFET

NCFET differs from conventional MOSFETs by the presence of ferroelectric material in gate stack. Ferroelectric material have a property of negative capacitance (described by Landau–Khalatnikov equation [17, 18]) which can be explained by charge versus voltage equation, mentioned in Eq. (4).

\(\alpha\), \(\beta\) and \(\gamma\) are anisotropy constant for ferroelectric materials, \(V_{F}\) and \(Q_{F}\) is voltage and charge across ferroelectric material. Schematic and capacitor model of 32 nm NCFET has been shown in Fig. 1a, b respectively. Models of NCFET have been obtained from Nano Hub [19], although we have modified it for undoped HfO_{2} which is mostly known for its high dielectric constant [20,21,22,23,24,25] when deposited with chemical vapor deposition behaves as ferroelectric [26,27,28]. The modification in the model is done by superseding existing anisotropy constant with anisotropy of undoped HfO_{2} which are calculated by relation mentioned in Eq. (5) [29]. Anisotropy constants are dependent on coercive field \((E_{C} )\) and remanent polarization \((P_{r} )\) of undoped HfO_{2} which are taken as 1000 kV/cm and 10 μC/cm^{2} respectively.

where \(V_{C}\) is coercive voltage and \(Q_{O}\) is remanent polarization charge in the ferroelectric material. From Fig. 1b under steady-state condition internal voltage can be expressed as:

where \(A_{G}\) is amplification factor and \(A_{D}\) is drain coupling factor in NCFET. Also \(V_{D}\) and \(V_{G}\) represents drain and gate voltage respectively and \(V_{MOS}\) represents the internal node voltage in NCFET. \(C_{MOS}\) represents total gate capacitance associated with underlying transistor whereas \(C_{S}\) and \(C_{D}\) represents gate to source capacitance and gate to drain capacitance respectively. It is visible, that amplification factor \((A_{G} )\) is higher when the ferroelectric capacitance \((C_{F} )\) and MOS capacitance \((C_{MOS} )\) are close to each other. Figure 2a shows charge versus capacitance characteristics, \(C_{F}\) and \(C_{MOS}\) are close to each other leading to the amplification factor in NCFET which can be seen in Fig. 2b. There is no amplification in MOSFET as \(A_{G} = 1\), which leads to \(V_{MOS} = V_{G}\) which is discussed in the further section.

## Performance analysis of NCFET

In this section, we have compared behaviour of MOSFET \((t_{FE} = 0\,{\text{nm}})\) and NCFET with \(t_{FE} = 10\,\,{\text{nm}}\) (considered ferroelectric is well below critical thickness hence hysteresis is not present in device characteristics). Figure 3a shows transfer characteristics of MOSFET and NCFET at \(V_{D} = 0.9\,{\text{V}}\). NCFET has \(78\%\) higher ON current and \(43\%\) lower OFF current compared to MOSFET hence \(212\%\) higher \(I_{ON} /I_{OFF}\) is obtained for NCFET. Increment in ON current is because of internal voltage amplification [30,31,32] provided by ferroelectric oxide which is due to positive feedback among the dipoles in ferroelectric material. Decrement in OFF current is because at \(V_{G} = 0\), \(V_{MOS}\) is negative (as shown in Fig. 3b) and hence leading to lower OFF current in NCFET Fig. 3c shows second-order transconductance characteristics of NCFET and MOSFET. Threshold voltage has been extracted from the second-order transconductance method [33]. Second-order transconductance method states that the value of gate voltage at which, maximum value of second-order transconductance value is achieved is threshold voltage of device. It is visible from Fig. 3c that the peak value of second-order transconductance is achieved at lower value gate bias for NCFET, which indicates the threshold voltage of NCFET is smaller as compared to conventional MOSFET. Detailed explanation for threshold voltage has discussed in below sub-section.

### Threshold Voltage

Threshold voltage can be defined as the applied gate voltage at which electron concentration in the channel region is equal to hole concentration in the substrate [34]. Threshold voltage for conventional MOSFET can be expressed as follows:

where \(V_{FB}\) is flat band voltage which can be defined as applied gate voltage at which no band bending in semiconductor exists, \(\phi_{fp}\) is built-in potential which can be expressed as \(\phi_{fp} = V_{T} \log N_{a} /n_{i}\), \(e\) is electronic charge, \(N_{a}\) is substrate doping, \(x_{dT}\) is maximum space charge width which can be expressed as \(x_{dT} = \sqrt {\left( {4\epsilon_{s} \phi_{fp} /eN_{a} } \right)}\) and \(C_{ox}\) is dielectric capacitance per unit area for MOSFET. Assuming flat band voltage and built-in potential is not affected by the presence of ferroelectric, threshold voltage only depends on \(eN_{a} x_{dT} /C_{ox}\). In NCFET equivalent oxide capacitance \((C_{ox }^{ '} )\) is series combination of dielectric capacitance (\(C_{ox}\)) and ferroelectric capacitance (\(C_{F}\)) which is mentioned in Eq. (2). Hence the threshold voltage of NCFET is given by:

Substituting the value of \(C_{ox }^{ '}\) from Eq. (2) in Eq. (10)

Hence it is evident that threshold voltage \((V_{TH}^{'} )\) of NCFET is lower as compared to MOSFET \(\left( {V_{TH} } \right)\). Ferroelectric capacitance is a strong function of ferroelectric thickness [35] and temperature [36], an increase in ferroelectric thickness leads to a decrease in ferroelectric capacitance, and hence threshold voltage decreases. Another reason for reduction in threshold voltage can be negative value of total oxide capacitance of NCFET which has been discussed above in Eq. (2). Also from Eq. (12), it is visible that at \(t_{FE} = 0\,{\text{nm}}\) threshold voltage of MOSFET is equal to the threshold voltage of NCFET.

### Drain-induced barrier lowering

Drain-induced barrier lowering (DIBL) is a short channel effect in MOSFET which is responsible for reduction of threshold voltage and an increase in leakage current at higher drain bias. Increase in drain bias increases the drain depletion width and it starts interacting with source and channel junction which hence reduces the barrier potential. As a result of a reduction in barrier potential electrons can easily be injected into the channel and gate voltage has no longer any control over the drain current. Figure 4a shows the transfer characteristics of MOSFET at \(V_{D} = 0.09\,{\text{V}}\) and \(V_{D} = 0.9\,{\text{V}}\). Increase in OFF and ON current for MOSFET, can be observed at \(V_{D} = 0.9\,{\text{V}}\). Increase in leakage current is because of reduction in threshold voltage which has been computed from second-order transconductance characteristics of MOSFET, shown in Fig. 4b dependence of threshold on drain bias in MOSFET be expressed as follows:

where \(\eta\) is DIBL factor and \(V_{TH0}\) is threshold voltage at zero drain bias. Since the DIBL factor is positive in case of MOSFET threshold voltage at \(V_{D} = 0.9\,{\text{V}}\) is smaller as compared to \(V_{D} = 0.09\,{\text{V}}\). DIBL can be computed from the expression mentioned below:

where \(V_{TH}^{H}\) and \(V_{TH}^{L}\) are threshold voltages at higher and lower drain bias respectively and \(V_{D}^{H}\) and \(V_{D}^{L}\) are higher and lower drain bias. This expression leads to a positive DIBL factor for MOSFET.

Similarly, DIBL has been studied for NCFET, but first, we look into the effect of drain bias variation on internal node voltage of NCFET. It is visible from Eq. (7) that \(V_{MOS}\) is dependent on both gate and drain bias. For \(V_{D} = 0.09\,{\text{V}}\) internal node voltage \((V_{MOS} )\) has a small positive value at \(V_{G} = 0\) while for \(V_{D} = 0.9\,{\text{V}}\) internal node voltage \((V_{MOS} )\) has a small negative value, this can be seen from Fig. 4c. Figure 4d shows the transfer characteristics of NCFET at \(V_{D} = 0.09\,{\text{V}}\) and \(V_{D} = 0.9\,{\text{V}}\). Decrease in OFF current for NCFET can be observed at \(V_{D} = 0.9\,{\text{V}}\). This decrement in leakage current is because the internal node voltage has a negative value at \(V_{D} = 0.9\,{\text{V}}\) while it has a positive value at \(V_{D} = 0.09\,{\text{V}}\). Further, we have computed threshold voltage for NCFET using second-order transconductance method. Figure 4e clearly shows that the threshold voltage for \(V_{D} = 0.9\,{\text{V}}\) is higher compared to \(V_{D} = 0.09\,{\text{V}}\) which is because of the negative value of DIBL factor in NCFET (see Eq. 15 for explanation).

In NCFET, barrier height increases with an increase in drain voltage, hence threshold voltage increases with increasing drain voltage which is opposite to that of MOSFET (in which threshold voltage decreases with increasing drain bias). This hence leads to a negative DIBL factor. DIBL factor has been computed for MOSFET and NCFET which is explicitly mentioned in Table 1.

## Conclusion

In this paper, we have studied threshold voltage and DIBL in MOSFET and NCFET. It has been observed that threshold voltage is smaller in NCFET when compared to MOSFET which is because of negative equivalent oxide capacitance in NCFET. We have also investigated drain induced barrier lowering in MOSFET and NCFET; it has been observed that an increase in drain bias in MOSFET, leads to a decrease in threshold voltage and an increase in leakage current, which hence leads to a positive value of DIBL factor. Also, an increase in drain bias in NCFET leads to an increase in threshold voltage and a decrease in leakage current, which hence leads to a negative value of the DIBL factor.

## References

- 1.
A. Jain, M.A. Alam, Stability constraints define the minimum subthreshold swing of a negative capacitance field-effect transistor. IEEE Trans. Electron Dev.

**61**(7), 2235–2242 (2014). https://doi.org/10.1109/TED.2014.2316167 - 2.
T. Yuan, T.H. Ning,

*Fundamentals of Modern VLSI Devices*(Cambridge University Press, Cambridge, 1998) - 3.
V.V. Zhirnov, R.K. Cavin, Nanoelectronics: Negative capacitance to the rescue? Nat. Nanotechnol.

**3**(2), 77–78 (2008). https://doi.org/10.1038/nnano.2008.18 - 4.
A.I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S.R. Bakaul, R. Ramesh, S. Salahuddin, Negative capacitance in a ferroelectric capacitor. Nat. Mater.

**14**(2), 182–186 (2015). https://doi.org/10.1038/nmat4148 - 5.
A.I. Khan, D. Bhowmik, P. Yu, S.J. Kim, X. Pan, R. Ramesh, S. Salahuddin, Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures. Appl. Phys. Lett.

**99**(11), 113501 (2011). https://doi.org/10.1063/1.3634072 - 6.
D.J.R. Appleby, N.K. Ponon, S.K.K. Kwa, B. Zou, P.K. Petrov, T. Wang, N.M. Alford, A. O’Neill, Experimental observation of negative capacitance in ferroelectrics at room temperature. Nano Lett.

**14**(7), 3864–3868 (2014). https://doi.org/10.1021/nl5017255 - 7.
S. Salahuddin, S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett.

**8**(2), 405–410 (2008). https://doi.org/10.1021/NL071804G - 8.
C.W. Yeung, A.I. Khan, A. Sarker, S. Salahuddin, C. Hu, Low power negative capacitance FETs for future quantum-well body technology, in

*2013 International Symposium on VLSI Technology, Systems and Application (VLSI*-*TSA)*, Hsinchu, pp. 1–2 (2013). https://doi.org/10.1109/vlsitsa.2013.6545648 - 9.
G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, Y.S. Chauhan, Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—part II: model validation. IEEE Trans. Electron Dev.

**63**(12), 4986–4992 (2016). https://doi.org/10.1109/ted.2016.2614436 - 10.
A. Sharma, K. Roy, Design space exploration of hysteresis-free HfZrOx-based negative capacitance FETs. IEEE Electron. Dev. Lett.

**38**(8), 1165–1167 (2017). https://doi.org/10.1109/LED.2017.2714659 - 11.
J. Seo, J. Lee, M. Shin, Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Trans. Electron Dev.

**64**(4), 1793–1798 (2017). https://doi.org/10.1109/TED.2017.2658673 - 12.
C. Jin, T. Saraya, T. Hiramoto, M. Kobayashi, Transient negative capacitance as cause of reverse drain-induced barrier lowering and negative differential resistance in ferroelectric FETs. VLSI Technol. Symp.

**2019**, 220–221 (2019) - 13.
Y. Peng, W. Xiao, G. Han, J. Wu, H. Liu, Y. Liu, N. Xu, T.K. Liu, Y. Hao, Nanocrystal-embedded-insulator ferroelectric negative capacitance FETs with sub-kT/q swing. IEEE Electron Dev. Lett.

**40**, 9‒12 (2018) - 14.
J. Zhou, G. Han, J. Li, Y. Liu, Y. Peng, J. Zhang, Negative differential resistance in negative capacitance FETs. IEEE Electron Dev. Lett.

**39**(4), 622–625 (2018) - 15.
J. Zhou, G. Han, Q. Li, Y. Peng, X. Lu, C. Zhang, J. Zhang, Q.Q. Sun, D.W. Zhang, Y. Hao, Ferroelectric HfZrO

_{x}; Ge and GeSn PMOSFETs with Sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved I, in*2016 IEEE International Electron Devices Meeting (IEDM)*(2016), pp. 12.2.1–12.2.4 - 16.
B. Awadhiya, P.N. Kondekar, A.D. Meshram, Understanding negative differential resistance and region of operation in undoped HfO

_{2}-based negative capacitance field effect transistor. Appl. Phys. A Mater. Sci. Process. (2019). https://doi.org/10.1007/s00339-019-2718-2 - 17.
L.D. Landau, I.M. Khalatnikov, On the anomalous absorption of sound near a second order phase transition point, in

*Collected Papers of L.D. Landau*(Elsevier, Amsterdam, 1965), pp. 626–629. https://doi.org/10.1016/b978-0-08-010586-4.50087-0 - 18.
T.K. Song, Landau–Khalatnikov simulations for ferroelectric switching in ferroelectric random access memory application. J.-Korean Phys. Soc.

**46**(1), 5–9 (2005) - 19.
M.A. Wahab, M.A. Alam, A verilog—a compact model for negative capacitance FET. (Version 1.1.3). nanoHUB (2017). https://doi.org/10.4231/d3qz22k3z

- 20.
N.P. Maity, R. Maity, R.K. Thapa, S. Baishya, A tunneling current density model for ultra thin HfO

_{2}high-k dielectric material based MOS devices. Superlattices Microstruct.**95**, 24–32 (2016). https://doi.org/10.1016/j.spmi.2016.04.032 - 21.
N.P. Maity, R. Maity, S. Baishya, Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO

_{2}based MOS devices. Superlattices Microstruct.**111**, 628–641 (2017). https://doi.org/10.1016/j.spmi.2017.07.022 - 22.
N.P. Maity, R. Maity, S. Maity, S. Baishya, Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation. J. Comput. Electron.

**18**(2), 492–499 (2019). https://doi.org/10.1007/s10825-018-01294-z - 23.
N.P. Maity, R. Maity, S. Baishya, An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J. Comput. Electron.

**18**(1), 65–75 (2019). https://doi.org/10.1007/s10825-018-1279-5 - 24.
S. Yadav, D. Sharma, D. Soni, M. Aslam, Controlling of ambipolarity with improved RF performance by drain/gate workfunction engineering and using high-k dielectric material in electrically doped TFET: proposal and optimization. J. Comput. Electron.

**16**, 721–731 (2017). https://doi.org/10.1007/s10825-017-1019-2 - 25.
S. Yadav, M. Aslam, D. Soni, D. Sharma, A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar. Behav. Superlattices Microstruct.

**117**, 9–17 (2018). https://doi.org/10.1016/j.spmi.2018.02.005 - 26.
P. Polakowski, J. Muller, Ferroelectricity in undoped hafnium oxide. Appl. Phys. Lett.

**106**(23), 232905 (2015). https://doi.org/10.1063/1.4922272 - 27.
K.D. Kim, M.H. Park, H.J. Kim, Y.J. Kim, T. Moon, Y.H. Lee, S.D. Hyun, T. Gwon, C.S. Hwaung, Ferroelectricity in undoped-HfO

_{2}thin films induced by deposition temperature control during atomic layer deposition. J. Mater. Chem. C**4**(28), 6864–6872 (2016). https://doi.org/10.1039/C6TC02003H - 28.
B. Awadhiya, P.N. Kondekar, A.D. Meshram, Investigating undoped HfO

_{2}as ferroelectric oxide in leaky and non-leaky FE–DE heterostructure. Trans. Electr. Electron. Mater.**20**(5), 467–472 (2019). https://doi.org/10.1007/s42341-019-00137-3 - 29.
A.I. Khan, U. Radhakrishna, K. Chatterjee, S. Salahuddin, D.A. Antoniadis, Negative capacitance behavior in a leaky ferroelectric. IEEE Trans. Electron Dev.

**63**(11), 4416–4422 (2016). https://doi.org/10.1109/TED.2016.2612656 - 30.
B. Obradovic, T. Rakshit, R. Hatcher, J.A. Kittl, M.S. Rodder, Ferroelectric switching delay as cause of negative capacitance and the implications to NCFETs, in

*2018 IEEE Symposium on VLSI Technology*(Honolulu, HI, 2018), pp. 51–52. https://doi.org/10.1109/VLSIT.2018.8510628 - 31.
B. Awadhiya, P.N. Kondekar, A.D. Meshram, Effect of ferroelectric thickness variation in undoped HfO

_{2}-based negative-capacitance field-effect transistor. J. Electron. Mater. (2019). https://doi.org/10.1007/s11664-019-07483-1 - 32.
H. Wang, M. Yang, Q. Huang, K. Zhu, Y. Zhao, Z. Liang, C. Chen, Z. Wang, Y. Zhong, X. Zhang, R. Huang, New insights into the physical origin of negative capacitance and hysteresis in NCFETs, in

*2018 IEEE International Electron Devices Meeting (IEDM)*(San Francisco, CA, 2018), pp. 31.1.1–31.1.4 https://doi.org/10.1109/iedm.2018.8614504 - 33.
A. Ortiz-Conde, F.J. Garcı́a, J.J. Liou, A. Cerdeira, M. Estrada, Y. Yue, A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliabil.

**42**(4–5), 583–596 (2002). https://doi.org/10.1016/s0026-2714(02)00027-6 - 34.
D. Neamen,

*Semiconductor Physics and Devices*(McGraw-Hill, New York, 2003) - 35.
B. Awadhiya, P.N. Kondekar, A.D. Meshram, Passive voltage amplification in non-leaky ferroelectric–dielectric heterostructure. Micro Nano Lett.

**13**(10), 1399–1403 (2018). https://doi.org/10.1049/mnl.2018.5172 - 36.
B. Awadhiya, P.N. Kondekar, A.D. Meshram, Analogous behavior of FE–DE heterostructure at room temperature and ferroelectric capacitor at Curie temperature. Superlattices Microstruct.

**123**, 306–310 (2018). https://doi.org/10.1016/J.SPMI.2018.09.015

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## Appendix

### Appendix

To understand the effect of gate \((V_{G} )\) and drain \(\left( {V_{D} } \right)\) bias on internal node voltage \((V_{MOS} )\), we need to study the equivalent capacitor model for NCFET shown in Fig. 5.

Considering \(V_{D} = 0\) and applying KCL at node \(V_{MOS}^{a}\) leads to following equation:

Solving the Eqs. (16) and (17)

Considering the negative nature of the ferroelectric capacitor \(V_{MOS}\) can be represented as:

Considering \(V_{G} = 0\) and applying KCL at node \(V_{MOS}^{b}\) leads to the following equation:

Since the condition for no hysteresis in NCFET is \(C_{MOS} < \left| {C_{F} } \right|\) and to achieve sub-60 mV/decade subthreshold swing condition is \(C_{ox} > \left| {C_{F} } \right|\). Now to achieve both the advantages the conditions become \(C_{MOS} < \left| {C_{F} } \right| < C_{ox}\). Since \(C_{ox}\) is greater than \(C_{MOS}\). Equation (20) can be approximated as \(C_{MOS} = C_{S} + C_{D} + C_{dep}\). Hence Eq. (23) can be written as:

Considering the negative nature of the ferroelectric capacitor \(V_{MOS}\) can be represented as:

\(V_{MOS}\) can be expressed as follows:

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Awadhiya, B., Kondekar, P.N., Yadav, S. *et al.* Insight into Threshold Voltage and Drain Induced Barrier Lowering in Negative Capacitance Field Effect Transistor.
*Trans. Electr. Electron. Mater.* (2020). https://doi.org/10.1007/s42341-020-00230-y

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### Keywords

- Subthreshold swing (SS)
- Negative capacitance field effect transistor (NCFET)
- Drain induced barrier lowering (DIBL)