Abstract
Time-sensitive networking (TSN) supports the integration of standard Ethernet and industrial control networ k by providing differential quality of service (QoS). A priority scheduler is typically the central component of TSN switches for QoS. Furthermore, TSN must deal with various requirements from various domains. As a result, an FPGA-based solution becomes one of the most promising solutions for TSN switches due to its programmability and customizability. But, resource usually becomes a bottleneck in such a solution. This study proposes a flattened-priority approach to develop a new resource-efficient priority scheduler called f-iSLIP by converting the widely used nonpriority scheduler, iSLIP. We implement f-iSLIP in our TSN switches and compare it with previous priority schedulers. It reduces the resource cost of lookup tables (LUTs) by 30–50% on average and the logic latency by 20–30% on average. Moreover, the throughput tests demonstrate that it prefers high priorities with no performance loss.
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Acknowledgements
This research is sponsored in part by the National Key Research and Development Program of China (No. 2018YFB1702600), in part by the Fundamental Research Funds for the Central Universities (No. 2019RC046) and the Project funded by China Postdoctoral Science Foundation (No. 2019M660439), and in part by the Dedicated Research Project of Wuhu (No. 2019DX03).
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Li, Z., Wan, H., Deng, Y. et al. A resource-efficient priority scheduler for time-sensitive networking switches. CCF Trans. Netw. 3, 21–34 (2020). https://doi.org/10.1007/s42045-020-00034-x
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DOI: https://doi.org/10.1007/s42045-020-00034-x