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ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods

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Abstract

Hardware Trojan (HT), intellectual property (IP) piracy, and overproduction of integrated circuit (IC) are three threats that may happen in untrusted fabrication foundries. HTs are malicious circuitry changes in the IC layout. They affect side-channels (IC parameters) such as path-delay or power consumption. Therefore, HT detection methods based on side-channel analysis have been proposed. They can detect an HT only if its effects on side-channels are significant among the alteration of side-channels, caused by process1 and environment2 variations. IC design modifications at different abstraction levels have been proposed to facilitate HT detection methods after fabrication, such as modifying a circuit to make the paths3 of the circuit more sensitive to HTs. Such modifications are known as design-for-trust (DfTr). In addition, key-based modifications have been proposed to protect IPs/ICs from IP piracy and IC overproduction. This approach is known as masking or obfuscation, and it modifies a circuit such that it does not correctly work without applying a correct key. In this work, we propose a DfTr method based on leveraging the masking approach. It improves HT detection methods based on path-delay analysis. As a matter of fact, the delay of shorter paths varies less than that of longer ones. Therefore, the objective of the proposed DfTr is to generate fake short paths for nets that only belong to long paths. Our layout level experiments show that the proposed DfTr masks the functionality of circuits and, on average, increases the HT detectability of path-delay-based detection methods by 10%.

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Notes

  1. ROs generate oscillations and they include an odd number of NOT gates (or gates having an inversion function such as NOR/NAND gates) and feedback that the output of the last NOT gate is fed into the first NOT gate.

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Authors and Affiliations

  1. Université Grenoble Alpes, Grenoble INP, LCIS: Laboratoire de Conception et d’Intégration des Systèmes, Valence, France

    Arash Nejat, David Hely & Vincent Beroulle

Authors
  1. Arash Nejat
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  2. David Hely
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  3. Vincent Beroulle
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Correspondence to Arash Nejat.

Additional information

1It is the variation of some transistor characteristics, such as channel length and oxide thickness, that happens during IC manufacturing.

2It is the variation of circuit operating environments, such as temperature and supply voltage, while the circuit is working.

3One path starts from a primary input or flip-flop and ends to a primary output or flip-flop.

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Nejat, A., Hely, D. & Beroulle, V. ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods. J Hardw Syst Secur 2, 83–96 (2018). https://doi.org/10.1007/s41635-018-0033-6

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  • DOI: https://doi.org/10.1007/s41635-018-0033-6

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