Skip to main content
SpringerLink
Log in

Security Measures Against a Rogue Network-on-Chip

  • Published:
Journal of Hardware and Systems Security Aims and scope Submit manuscript

Abstract

Network-on-chip facilitates glueless interconnection of various on-chip components in the forthcoming system-on-chips. As in the case of any new technology, security is a major concern in network-on-chip (NoC) design too. In this work, we explore a covert threat model for multiprocessor system-on-chips (MPSoCs) stemming from the use of malicious third-party network-on-chips (NoCs). We illustrate that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform. Further, to counter the threat posed by rNoC, we propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. We also discuss measures that can be taken to minimize the impact of a rNoC, once it is detected. Our comprehensive cross-layer analysis of our novel detection technique indicates modest overheads of 12.73% in area, 9.844% in power, and 5.4% in terms of network latency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Notes

  1. To eliminate obvious noise, we truncate the data at a minimum NLD of 6.

References

  1. SonicsMX SMART Interconnect Datasheet. http://www.http://sonicsinc.com/

  2. Abramovici M, Bradley P (2009) Integrated circuit security: new threats and solutions CSIIRW, p 55

    Google Scholar 

  3. Alves T, Felton D (2004) TrustZone: integrated hardware and software security. ARM White Paper 3 (4):18–24

    Google Scholar 

  4. Ancajas DM, Chakraborty K, Roy S (2014) Fort-NoCs: mitigating the threat of a compromised NoC. pp 1–6

  5. Armbrust M, Fox A, Griffith R, Joseph AD, Katz RH, Konwinski A, Lee G, Patterson DA, Rabkin A, Stoica I, Zaharia M (2010) A view of cloud computing. ACM 53(4)

  6. Auerbach D Volkswagen’s villains. http://www.slate.com/articles/technology/bitwise/2015/10/volkswagen_s_emissions_scandal_has_a_villain_and_it_s_the_not_the_people.html

  7. Becker D (2012) Open source NoC router RTL. https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/Router

  8. Boraten T, Kodi AK (2016) Mitigation of denial of service attack with hardware trojans in NoC architectures 2016 IEEE international parallel and distributed processing symposium, IPDPS 2016, Chicago, IL, USA, May 23–27, 2016, pp 1091–1100

    Google Scholar 

  9. Diemer J, Ernst R (2010) Back suction: service guarantees for latency-sensitive on-chip networks. pp 155–162

  10. Diguet J.-P., Evain S, Vaslin R, Gogniat G, Juin E (2007) NOC-centric security of reconfigurable SoC. pp 223–232

  11. Fiorin L, Palermo G, Lukovic S, Catalano V, Silvano C (2008) Secure memory accesses on networks-on-chip. TC 57(9):1216–1229

    MathSciNet  Google Scholar 

  12. Fiorin L, Palermo G, Silvano C (2008) A security monitoring service for NoCs. pp 197–202

  13. Funk JL (2008) Systems, components and modular design: the case of the US semiconductor industry. IJTM 42(4):387–413

    Article  Google Scholar 

  14. Gartner Inc (2014) Semiconductor design IP revenue, chip infrastructure, worldwide 2012 and 2013. Gartner Research

  15. Gebotys CH, Gebotys RJ (2003) A framework for security on NoC technologies. pp 113–117

  16. Grot B, Hestness J, Keckler SW, Mutlu O (2011) Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees. pp 401–412

  17. Hestness J, Grot B, Keckler SW (2010) Netrace: dependency-driven trace-based network-on-chip simulation. ACM, pp 31–36

  18. Hoskote Y, Vangal SR, Singh A, Borkar N, Borkar S (2007) A 5-GHz mesh interconnect for a teraflops processor. IEEE MICRO 27(5):51–61

    Article  Google Scholar 

  19. Jiang N, Becker D, Michelogiannakis G, Balfour J, Towles B, Shaw D, Kim J, Dally W (2013) A detailed and flexible cycle-accurate network-on-chip simulator. pp 86–96

  20. Kapoor HK, Rao GB, Arshi S, Trivedi G (2013) A security framework for NoC using authenticated encryption and session keys. 1–18

  21. Kiasari AE, Lu Z, Jantsch A (2013) An analytical latency model for networks-on-chip. TVLSI 21 (1):113–123

    Google Scholar 

  22. Kim D, Yoo S, Lee S (2010) A network congestion-aware memory controller. IEEE, pp 257–264

  23. King ST, Tucek J, Cozzie A, Grier C, Jiang W, Zhou Y (2008) Designing and implementing malicious hardware. vol 8, pp 1– 8

  24. Liu C, Rajendran J, Yang C, Karri R (2013) Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. pp 101–106

  25. Misler M, Jerger NDE (2013) Moths: mobile threads for on-chip networks. TEC 12(1s):56

    Google Scholar 

  26. User, Assurance and Planning, Audit (1995) An Introduction to Computer Security: The NIST Handbook

  27. OCP International Partnership (2009) Open core protocol specification: Release 3.0

  28. Qian Z, Juan D, Bogdan P, Tsui C, Marculescu D, Marculescu R (2014) A comprehensive and accurate latency model for network-on-chip performance analysis. pp 323–328

  29. Sepúlveda J, Pires R, Strum M, Chau WJ (2010) Implementation of QoSS (quality-of-security service) for NoC-based SoC protection. Theor Comput Sci 10:187–201

    Google Scholar 

  30. Tehranipoor M, Koushanfar F (2010) A survey of hardware trojan taxonomy and detection. DTC 27 (1):10–25

    Google Scholar 

  31. Waksman A, Suozzo M, Sethumadhavan S (2013) FANCI: identification of stealthy malicious logic using Boolean functional analysis. pp 697–708

  32. Wang Y, Suh GE (2012) Efficient timing channel protection for on-chip networks. pp 142–151

  33. Wassel HMG, Gao Y, Oberg J, Huffmire T, Kastner R, Chong FT, Sherwood T (2013) SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip. pp 583– 594

  34. Wentzlaff D, Griffin P, Hoffmann H, Bao L, Edwards B, Ramey C, Mattina M, Miao C-C, Brown III JF, Agarwal A (2007) On-chip interconnection architecture of the tile processor. 15–31

  35. Wilson EB, Hilferty MM (1931) The distribution of chi-square. Proc Nat Acad Sci USA 17(12):684–688

    Article  MATH  Google Scholar 

Download references

Acknowledgments

This work was supported in part by the National Science Foundation grants (CNS-1117425, CAREER-1253024, CCF-1318826, CNS-1421022, CNS-1421068). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the NSF.

Author information

Authors and Affiliations

  1. USU BRIDGE LAB, Electrical and Computer Engineering, Utah State University, Logan, UT, USA

    Rajesh JayashankaraShridevi, Dean Michael Ancajas, Koushik Chakraborty & Sanghamitra Roy

Authors
  1. Rajesh JayashankaraShridevi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dean Michael Ancajas
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Koushik Chakraborty
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Sanghamitra Roy
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Rajesh JayashankaraShridevi.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

JayashankaraShridevi, R., Ancajas, D.M., Chakraborty, K. et al. Security Measures Against a Rogue Network-on-Chip. J Hardw Syst Secur 1, 173–187 (2017). https://doi.org/10.1007/s41635-017-0008-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s41635-017-0008-z

Keywords

Search

Navigation