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The application of digital technology in BEPCII RF system

  • Mu-Yuan Wang
  • Yi Sun
  • Guang-Wei Wang
  • Wei-Min Pan
  • Hai-Ying Lin
  • Qun-Yao Wang
  • Qiang Ma
  • Zhong-Quan Li
  • Jian-Ping Dai
  • Peng Sha
  • Zheng-Hui Mi
  • Hong-Lei Wang
  • Dan-Yang Zhao
Original Paper
  • 238 Downloads

Abstract

Background

The Beijing Electron Positron Collider (BEPCII) is a high-brightness collider and operates in compatible mode of synchronous light source. This summer, BEPCII spare cavity, which was all made in China, had been put into BEPCII operation, and the LLRF system for the spare cavity was also upgraded at the time.

Purpose

The purpose is to stably control the amplitude and phase of the spare cavity and apply digital technology to achieve some intelligent functions.

Methods

The digital method is applied in the superconducting cavity feedback control of the accelerator and it introduces the digital technology of the RF low-level control system that has been stably applied to the BEPCII spare cavity operation. In addition, some functions such as quench detector and input protection as well as horizontal test have been realized in the RF system operation.

Results

The amplitude and phase stabilities of cavity voltage with beam in the digital LLRF have reached \(\pm 0.09\%\) (RMS) and \(\pm 0.055^{\circ }\) (RMS), respectively.

Conclusion

The BEPCII spare cavity with digital LLRF system has been stably operated for 2 months. The DLLRF system has been reliable and stable, and the performance of the spare cavity with beam was very good.

Keywords

Digital low-level Radio frequency Spare cavity 

Introduction

The upgrade project of the Beijing Electron Positron Collider (BEPCII) is a double-ring high-brightness collider, and operating in compatible mode of synchronous light source. One ring has one RF station which is composed of a 250-kW klystron, a 500-MHz superconducting cavity and a low-level system. In Synchrotron Radiation mode, beam current is 250 mA, one RF station can provide 2.0 MV accelerating voltage and 100 kW RF power. In collision mode, beam current reaches 910 mA, and accelerating voltage of 1.5 MV and RF power of 150 kW are provided to the electron beam [1]. The main parameters of the SRF system are listed in Table 1.

This summer, BEPCII spare cavity which was all made in China had been put into BEPCII operation, and the low-level control system for this spare cavity was also upgraded at the same time. Digital technology has been applied instead of the analog system used for many years. Two-month operation shows the machine was stable and reliable, and the precisions of the amplitude and the phase of the digital feedback control meet the BEPCII operation requirements.

Hardware

The hardware of the digital low-level system mainly includes the analog front end and FPGA board. Firstly, the analog front end includes the local signal generation, reference and local signal splitter, and the up/down conversion module [2]. Figure 1 shows the analog front end.

A 499.8-MHz reference (REF) signal generated by a signal source is fed into a clock distribution AD9510 to generate IF signal as timing clock for ADC, DAC, and FPGA. For this application, the IF runs at one-sixteenth times reference, while the AD sampling clocks is five-fourth times IF and the DA sampling clocks is sixteen-fifth times IF. The IF is mixed with the REF to generate a LO signal which is used to down-convert the concerned RF signals to IF band and also to up-convert processed IF signals to RF band. Figure 2a and b shows that the channel amplitude and phase error (\(V_\mathrm{pp}\) & RMS) changes with the input value of ADC (mV) [3].
Table 1

Main parameters of the BEPCII SRF system

Parameters

Collision mode

SR mode

Frequency

499.8 MHz

499.8 MHz

Cavity voltage

1.5 MV

2.0 MV

Beam current

910 mA

250 mA

Beam power

123 kW

97 kW

Synchrotron phase

\(175^{\circ }\)

\(165^{\circ }\)

Amp stability (\(\triangle {V}_{\mathrm{c}}/{V}_{\mathrm{c}})\)

\(\pm \,\)1%

\(\pm \,\)1%

Phase stability (\(\triangle \Phi )\)

\(\pm \,1^{\circ }\)

\(\pm \,1^{\circ }\)

Fig. 1

Analog front end

Secondly, The Stratix-II EP2S60F1020I4 FPGA [3] is hosted on the FPGA board to implement the signal processing and control algorithm. The five high-speed ADC channels (LTC2255, 14 bits, 125 MPS maximum sampling rate) are used to sample the reference (REF), pick-up (\(P_\mathrm{t})\), forward (\(P_\mathrm{F})\), reflected (\(P_\mathrm{R})\), and the beam signal. All channel ADCs sampling data transfer to the IQ baseband signal with digital IQ demodulation. The IQ sequences of five channel signal are passed to the filter in order to obtain the stable IQ sequences and rotated or attenuated by IQ set value [4]. Next, the IQ error are passed to a PI controller implemented in FPGA, and the PI output are modulated by digital numerically controlled oscillator (NCO) to generate an IF signal digital waveform [5].

On the other hand, the soft core NIOS II is used as Avalon bus structure communicating with the host PC by a 10M Ethernet port mounted on the FPGA board and transmitted data which include cavity voltage amplitude and phase, forward power, reflected power, and beam current to the EPICS and stored in a database. The PI controller set value which includes proportional parameter and integral parameter both are given by EPICS and the digital NCO look-up table is generated by MATLAB codes [6].

Digital technology application on the spare cavity

The digital low-level control has replaced the traditional analog feedback control in the BEPCII spare cavity operated, while retained the original frequency control loop and fast interlock. The control loops of digital amplitude and phase are working well. Figure 3 shows the block diagram of the digital low-level technology application on the spare cavity.
Fig. 2

a Amplitude error with ADC different input, b the phase error with ADC different input

Fig. 3

Block diagram of the digital low-level technology application on the spare cavity

Fig. 4

a Changes of vacuum during cooldown, b the changes of frequency during cooldown

Fig. 5

Frequency load curve

Fig. 6

Horizontal test for BEPCII spare cavity (color figure online)

Horizontal test for BEPCII spare cavity

The digital technology can generate pulse wave, continuous wave, and saw-tooth wave, and the period amplitude and duty are adjustable by EPICS. BEPCII spare cavity was aged in both continuous wave and pulse wave at 4 K. During cooldown in the horizontal test, the frequency and vacuum of the spare cavity were monitored with a network analyzer and penning gauge separately. Figure 4a shows that the vacuum of the spare cavity improved during cooldown; Fig. 4b shows that the frequency of the spare cavity increased during cooldown. The frequency is 499.5 MHz at 5 K and the rate of change is approximately 2.278 kHz/K.

While the temperature down to 4.4 K, the tuner made the resonant frequency cavity to be 499.8 MHz, the change of the spare cavity frequency with load was measured by the network analyzer as shown in Fig. 5. It can be found that the spare cavity frequency has a linear relation with load, and the elastic coefficient of the cavity is about 938 Hz/kg [7].

Figure 6 shows the horizontal test for the spare cavity. Red line represents pulse aging for the cavity, and blue one represents continuous wave aging. Obviously, the performance of the cavity is improved after the pulse aging [8].

Figure 7 shows the radiation status during the spare cavity test. Radiation of the spare cavity cannot reduce through continuous wave aging (the blue, red, and green line, in this figure); however, radiation has been significantly descended by the pulse wave aging (purple line).

Cavity quench and protection

The function of the original analog quench detection and cavity protection were replaced by the digital low-level system. The unlimited input power can cause irreversible destruction to the RF parts such as breaking the ceramic window of input coupler and making damage for klystron by large power reflection. The quench can change spare cavity performance and result in big impact on the cryogenic system. Therefore, two kinds of protection functions with digital technology are applied, and the input power limitation is set to a reasonable value by EPICS program. These limitation settings were more operable and maneuverable than previous analog plug-in implementations. Figure 8 shows the block diagram of two protection functions.

Both methods were used in FPGA so as to realize fast interlock protection. Only if the input power is larger than limitation settings will the cavity protection activate immediately.

Quench protection under open-loop case will act by comparing the reflection power with the incident power, while in closed-loop case, when the cavity voltage is lower than the 80 percent of reference setting, the protection will be triggered. But if the spare cavity is pre-tuned under the closed loop, the protection will not work even if it meets the trigger condition. Figure 9 shows the test for the protection function.

Figure 9a shows the results of the cavity protection, when the sum of squares for dds_i and dds_q (blue line) reaches the power threshold (red line), the protection will be carried out and reference setting will be back to original value. Figure 9b and c shows the quench protection in opened or closed loop, if meeting the trigger condition, the protection program will cut off incident power (red-lines) in next cycle. The functions above have been proved to be effective and reliable through experiments and the formal operation.
Fig. 7

Radiation test for the spare cavity (color figure online)

Fig. 8

Block diagram of two protection functions

Fig. 9

a Test for the cavity protection, b, c open-loop/close-loop test for quench protection (color figure online)

Fig. 10

a Error of amplitude for cavity voltage with \({K}_{\mathrm{i}}\) scanning, b the error of phase for cavity voltage with \({K}_{\mathrm{i}}\) scanning

PI scanning

At present, the digital low-level system has been used to control the cavity with current beam, and the cavity voltage could obtain higher SNR and lower phase noise by selecting optimized PI parameter in closed loop. Figure 10 shows the error of cavity voltage amplitude and phase for PI controller which \({K}_{\mathrm{i}}\) scanning and \({K}_{\mathrm{P}}\) is constant (\({K}_{\mathrm{P}} = 0.8\)), and the working point is expressed by the blue point.

Figure 11 shows the error of cavity voltage amplitude and phase for PI controller with \({K}_{\mathrm{P}}\) scanning and \({K}_{\mathrm{i}}\) is constant (\({K}_{\mathrm{i}} = 0.0008\)), the working point is also expressed by the blue point.
Fig. 11

a Error of amplitude for cavity voltage with \({K}_{\mathrm{P}}\) scanning, b the error of phase for cavity voltage with \({K}_{\mathrm{P}}\) scanning

Results and discussion

The following figures display the EPICS control interface and PLC monitoring interface in RF system. The former is the status of the spare cavity controlled by reading and writing the registers in FPGA, and the latter clearly shows some important physical quantities from the cavity to monitor, such as cavity voltage, vacuum, and cryogenics. In addition, we also monitor in real time the radiation dose of the cavity by dosimeter and dump data to the archiver database by serial server and EPICS (Fig. 12).

Amplitude and phase of the spare cavity voltage were monitored and recorded by EPICS. Figure 13a shows the precision of amplitude and phase from digital low-level system, and Fig. 13b shows the histogram of the amplitude and phase.

It is shown from above figures that the spare cavity amplitude stabilities are \(\pm \,0.665\%\) (\(V_\mathrm{pp})\) and \(\pm \,0.09\%\) (RMS) respectively, and the phase stabilities are \(\pm \,0.427^{\circ }(V_\mathrm{pp})\) and \(\pm \,0.055^{\circ }\)(RMS). By contrast, the precision of amplitude and phase in cavity voltage through digital control is better than analog.

Summary

BEPCII spare cavity with digital low-level system has been stably operated for 2 months. The performance of the spare cavity with beam was very well and the digital low-level system has been stable and reliable, which satisfies BEPCII operation requirements.
Fig. 12

EPICS control interface and PLC monitor interface

Fig. 13

a Precision of amplitude and phase in the spare cavity with beam, b the histogram of amplitude and phase in the spare cavity with beam

References

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Copyright information

© Institute of High Energy Physics, Chinese Academy of Sciences; China Nuclear Electronics and Nuclear Detection Society and Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Mu-Yuan Wang
    • 1
    • 2
  • Yi Sun
    • 2
  • Guang-Wei Wang
    • 2
  • Wei-Min Pan
    • 1
    • 2
  • Hai-Ying Lin
    • 2
  • Qun-Yao Wang
    • 2
  • Qiang Ma
    • 2
  • Zhong-Quan Li
    • 2
  • Jian-Ping Dai
    • 2
  • Peng Sha
    • 2
  • Zheng-Hui Mi
    • 2
  • Hong-Lei Wang
    • 1
    • 2
  • Dan-Yang Zhao
    • 3
  1. 1.University of Chinese Academy of SciencesBeijingChina
  2. 2.Institute of High Energy PhysicsCASBeijingChina
  3. 3.China National Electronics Import & Export Corporation (CEIEC)BeijingChina

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