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Design and simulation of graphene logic gates using graphene p–n junctions as building blocks

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Abstract

Electrostatically doped graphene p–n junctions can modulate graphene nanoribbon conductance and can be indispensable parts of nanoelectronic graphene circuits. Much research has been conducted on such devices with one rectangular top gate and one back gate with very encouraging results. Recently, graphene p–n junctions with two rectangular top gates have been proposed and their study revealed a rich behaviour that allows their use in both analogue and digital nanoelectronic circuits. Here we study graphene p–n junctions with two trapezoid top gates and a common back gate with special focus to the effect of the angle and the distance between the two top gates. Furthermore, trapezoid top gates with angles of 45° make use of the Veselago lens effect, allowing an effective control by tuning density of states and carrier density. We simulated these devises using the non-equilibrium Green’s function method combined with tight-binding Hamiltonians in the ballistic transport limit. Our results show that the conductance of these graphene p–n junctions can be successfully controlled by various combinations of different parameters that allows for realisation of carbon-based logic gates. We also present the design and simulation a universal set Boolean gates, namely NOT, NAND and NOR.

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source and drain contacts as well as the substrate are usually much larger than the actual ribbon in physical devices

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine, Kensington, London, SW7 2AZ, UK

    Ioannis Nikiforidis

  2. Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Kimmeria, Xanthi, Greece

    Ioannis G. Karafyllidis & Georgios Ch. Sirakoulis

  3. Institute of Nanoscience and Nanotechnology, NCSR “Demokritos”, PO Box 60033, 15310, Aghia Paraskevi Attica, Greece

    Ioannis G. Karafyllidis & Panagiotis Dimitrakis

Authors
  1. Ioannis Nikiforidis
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  2. Ioannis G. Karafyllidis
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  3. Panagiotis Dimitrakis
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  4. Georgios Ch. Sirakoulis
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Correspondence to Ioannis G. Karafyllidis.

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Nikiforidis, I., Karafyllidis, I.G., Dimitrakis, P. et al. Design and simulation of graphene logic gates using graphene p–n junctions as building blocks. Graphene and 2D Materials Technol 6, 35–47 (2021). https://doi.org/10.1007/s41127-021-00043-7

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  • DOI: https://doi.org/10.1007/s41127-021-00043-7

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