Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications
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In this paper, a gallium antimonide junctionless tunnel field-effect transistor based on electrically doped concept (GaSb–EDTFET) is studied and simulated. The performance of the device is analyzed based on the energy band diagram and electric field profile. The on-current, transconductance, and cut-off frequency are enhanced in case of GaSb–EDTFET compared with Si-EDTFET due to the combination of the high tunneling efficiency of the narrow bandgap and the high-electron mobility of GaSb. On the other hand, the Gaussian-doping profile decreases the ambipolar and off current by increasing the tunneling barrier length at the drain/channel interface. Hence, applying Gaussian-doping profile on GaSb–EDTFET makes it a suitable candidate for analog and digital applications. Next, heterostructure channel/source interface EDTFET is studied which uses GaSb for the source and AlGaSb for the drain and channel regions. Then, it has been optimized by numerical simulation in terms of aluminum (Al) composition. The optimal Al composition was founded to be around 10% (x = 0.1). It is shown that the blend of Gaussian-doping profile and the heterostructure channel/source interface with optimal Al composition remarkably reduces ambipolar current amount to a value of 1.3 × 10−23 A/μm. The improvements in terms of Ioff, Ion, Ion/Ioff rate, subthreshold swing, transconductance, cut-off frequency, and also suppressed ambipolar behavior are illustrated by numerical simulations.
KeywordsElectrically doped tunnel field-effect transistor Ambipolar current Gaussian doping Heterostructure
In recent years, the scaling of conventional CMOS transistors and supply voltage have been faced with problems such as high off-state current, SCEs, DIBL, and subthreshold swing limits of 60 mV/dec at room temperature [1, 2, 3]. Therefore, some various device structures such as double gate , tri-gate , gate-all-around (GAA) MOSFET , and junctionless field-effect transistor JLFET  have been reported. JLFET has been fabricated without using PN junctions at the lateral junctions. Although it simplifies the fabrication process, it also suffers from the high off-state current. Tunneling field-effect transistors (TFETs) recently replaced the conventional MOSFET due to its steeper subthreshold swing (SS) (< 60 mV/dec) and low off-state current (Ioff) which leads to the low values of power consumption [8, 9, 10, 11, 12]. The achievement was obtained due to the band-to-band tunneling (BTBT) carriers rather than drift–diffusion over the barrier. One of the drawbacks of the performance of TFETs is the inferior on-state current (Ion) because of the insufficient quantum BTBT limited by the large bandgap of silicon. Hence, it can be solved using low bandgap semiconductors . Lately, different methods of improving the performance of TFETs have been presented such as gate engineering , using heterostructures and high-k dielectric . TFETs also suffer from ambipolar behavior [16, 17], which is concluded from the presence of symmetric areas of P+ and N+ in the source and the drain, the overlapping between the valence band of the channel, and the conduction band of the drain under negative gate bias. In this condition, the channel is accumulated by holes due to BTBT at drain/channel interface. Therefore, it has created a high current drive at the negative voltage similar to the positive voltage. To overcome the ambipolar behavior, researchers have used hetero-gate dielectrics, gate workfunction engineering, asymmetric doping for source and drain , Gaussian-doping profiles, and gate–drain overlapping [14, 16, 17, 19, 20, 21, 22].
Another drawback in the down-scaling process of TFETs is to fabricate metallurgical junctions due to the need for the creation of abrupt junctions at high temperatures which is difficult and expensive . This problem can be solved using junctionless TFETs (JLTFETs) [22, 23]. JLTFET uses high-doping concentrations in the drain, channel, and source. It has provided N+–I–P+ for N-JLTFETs similar to doping profile of an N-TFET using two methods. One method is the use of the charge plasma concept, wherein the desired doping profile is created by choosing appropriate workfunctions for the gates called the polarity gate (PG) located at the source region and the control gate (CG) located at the middle with a lower workfunction than PG for being a nearly intrinsic channel [24, 25, 26, 27]. As the same way, p-channel JLTFET has the similar structure . Another method to create N+–I–P+ in JLTFET is using the electrically doped concept, in which P+ region underneath PG is created by applying an appropriate external bias voltage. These devices are known as EDTFET [29, 30, 31]. The other type of JLTFETs known as dopingless TFETs suppresses the need of a higher thermal budget and expensive thermal annealing technique due to refusing the physical doping [32, 33, 34, 35, 36]. In this structure, the drain region is also gated for creating N+ using charge plasma or electrically doped concepts. JLTFETs also include inferior Ion and ambipolar behavior. To overcome these problems, different methods have been investigated, such as: using heterostructures at source/channel interfaces [37, 38, 39, 40, 41], the assumption of gate workfunction engineering [42, 43, 44, 45], the adoption of hetero-gate dielectrics [46, 47, 48, 49], using Gaussian-doping profiles [22, 50, 51], applying source pockets , the consideration of strain engineering [53, 54], using ferroelectric insulators , and drain workfunction engineering for DLTFET [55, 56].
The rest of this paper is structured as follows. In Sect. 2, device simulations and structures are discussed. In Sect. 3, the DC characteristics for the GaSb–EDTFET are presented which clarify its improvements in analog applications over a basic Si-EDTFET. In Sect. 4, Gaussian-doping distribution is proposed to decrease the ambipolar current. Section 5 is dedicated to the analysis and calculation of analog parameters, cut-off frequency, and transconductance for the GD–GaSb–EDTFET. In Sect. 6, heterostructure channel/source interface EDTFET is studied which applies AlxGa1−xSb for the channel and drain regions and GaSb for the source region (AlGaSb–GaSb–EDTFET). With respect to the Al fraction (x), the bandgap energy of AlxGa1-xSb and, consequently, the tunneling probability and the device current vary. Thus, the optimal Al composition is extracted in AlGaSb based on the improving ambipolar current, off-current, on-current, on-to-off current ratio, threshold voltage, and subthreshold swing. Then, it is presented a performance comparison between the structures in DC parameters is presented. Section 7 concludes this paper.
Device structure and simulation
Device design parameters used in simulation
Gate length (Lch)
Equivalent oxide thickness (EOT)
Spacer length between CG and PG (Lgap)
Silicon thickness (Tsi)
Polarity gate (PG)
Dielectric constant (hfo2)
All the electrical characteristics were obtained from 2D ATLAS device simulator . A nonlocal BTBT model to calculate band-to-band tunneling of charge carriers between source and channel was included. In this model, the spatial variation of energy bands is taken into account and also the recombination–generation rate at each location is considered based on the electric field to model the tunneling process. The Shockley–Read–Hall model was also used to incorporate the minority recombination due to the presence of high-impurity concentration in the channel and the interface trap effect. It takes into consideration the phonon transitions that occur in the presence of defects or traps within the forbidden gap of the semiconductor. Fermi–Dirac statistics was invoked to calculate the intrinsic carrier concentration required in the expressions for SRH recombination. Auger recombination is a non-radiative process involving three carriers. It occurs when an electron and hole recombine, but instead of producing light, either an electron is raised higher into the conduction band or a hole is pushed deeper into the valence band. Auger recombination is significant in non-equilibrium conditions when the carrier density is very high. To consider this effect, auger recombination model was included. High doping often leads to narrowing of bandgap and is essential to consider especially within the devices which are based on tunneling mechanism. Therefore, bandgap narrowing model is also incorporated. The quantum confinement model was activated to consider quantum confinement effects on BTBT.
In this section, the analog performance of the GD–GaSb–EDTFET compared to the conventional EDTFET is analyzed. Cut-off frequency (fT) and transconductance (gm) of the structures are obtained and compared. The parameter gm is the ratio of the variation in the drain current to the variation in the gate voltage of the device. By increasing the gate–source voltage, the number of electrons injected from the source\channel interface is incremented due to the quantum-tunneling phenomenon; therefore, the gm parameter is increased which has the significant role to determine cut-off frequency.
In the following, the combination of the two above methods, heterostructure and Gaussian-doping profile, on EDTFET (GD–Al0.1GaSb–GaSb–EDTFET) is investigated and DC parameters’ device is obtained using the extract of transfer characteristic (Id-Vgs). SSp is 37 mV/dec, Ion is 6.2 × 10−5 A/μm, Ioff is 1.7 × 10−19 A/μm, Ion/Ioff ratio is 3.6 × 1014, and Iamb is 1.3 × 10−23 A/μm. Therefore, it is clear that Iamb has declined sharply.
Obtained parameters of the proposed devices and conventional EDTFET
SS Point (mV/dec)
SS average (mV/dec)
Threshold voltage (V)
Ambipolar current (A/μm)
Off current (A/μm)
3.6 × 10−17
6.7 × 10−17
5.7 × 10−6
0.8 × 1011
9.9 × 10−19
1.2 × 10−18
2.5 × 10−4
2.1 × 1014
1.3 × 10−23
1.7 × 10−19
6.2 × 10−5
3.6 × 1014
In this paper, a junctionless tunnel field-effect transistor was simulated based on electrically doped concept using two-dimensional Silvaco TCAD. To increase on-state current, GaSb, a III–V semiconductor, was used which has narrow bandgap and high carrier mobility. On-state current with a value of 0.25 mA/μm at Vds = 1 V and Vgs = 1.2 V in case of GaSb–EDTFET was found to increase significantly compared to the conventional EDTFET. Then, the Gaussian-doping profile was used to reduce Ioff and Iamb. Wherein Iamb is 9.9 × 10−19 A/μm, Ioff is 1.2 × 10−18 A/μm, Ion is 2.5 × 10−4 A/μm, Ion/Ioff ratio is 2.1 × 1014, and the subthreshold swing (SS) is 56 mV/dec. In the process of improving the performance of the device at both the analog and digital applications, heterostructure source/channel interface was used; therefore, GaSb was allocated to source and AlGaSb to channel and drain regions. Then, the optimal Al composition for AlGaSb was founded to be around 10% (x = 0.1) by trading-off DC characteristics. The next Gaussian-doping profile was used in drain and channel. This Gaussian structure called the GD–Al0.1GaSb–GaSb–EDTFET has Iamb of 1.3 × 10−23 A/μm, Ioff of 1.7 × 10−19 A/μm, Ion of 6.2 × 10− 5 A/μm, the Ion/Ioff ratio of 3.6 × 1014, and SS of 37 mV/dec, which has a remarkable improvement over the conventional Si-EDTFET. fT and gm of devices were also investigated and the results demonstrated that the proposed devices were significantly better as compared with the conventional EDTFET. According to the numerical simulations, these proposed devices can also be the suitable candidates for analog and digital applications.
- 5.Kim, S.H., Yokoyama, M., Nakane, R., Ichikawa, O., Osada, T., Hata, M., Takenaka, M., Takagi, S.: High performance tri-gate extremely thin-body InAs-on-insulator MOSFETs with high short channel effect immunity and V th tunability. IEEE Trans. Electron Dev. 61(5), 1354–1360 (2014)CrossRefGoogle Scholar
- 42.Cecil, K., Singh, J.: Performance enhancement of dopingless tunnel-FET based on Ge-source with high-k. IEEE International Symposium on Nanoelectronic and Information Systems, pp.19–22 (2015)Google Scholar
- 58.Yogesh, G., Pranav, A., Bahniman, G.: Nanoscale III–V on Si-based junctionless tunnel transistor for EHF band applications. Nanoscale 38(5), 054002 (2017)Google Scholar
- 60.Silvaco Inc.: Atlas User’s Manual. Silvaco Inc., Santa Clara (2017)Google Scholar
- 61.Sze, S.M., Ng, K.K.: Physics of Semiconductor Devices. Wiley (2007)Google Scholar
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