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TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

  • Original Paper - Condensed Matter
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Abstract

In this study, we propose a ferroelectric FET (FeFET) structure termed dual ferroelectric recessed channel FeFET (DF-RFeFET), employing metal–ferroelectric (FE)–metal–FE–metal–SiO2 interlayer (IL)–silicon (MFMFMIS) structures. The DF-RFeFET is aimed at enhancing the memory window (MW) for high-performance memory applications. TCAD simulations with calibrated FE parameters and device models reveal that the DF-RFeFET can achieve a larger MW thanks to the enhanced geometric advantage to offer a strong and localized electric field at the inner ferroelectrics near the gate metal’s corner. Moreover, design guidelines for the DF-RFeFET are suggested, including adjusting the inner and outer ferroelectric layers' thickness ratio and the recessed channel depth. The effects of introducing a relatively low-k oxide intermediate layer between dual ferroelectric layers and high-k gate stacks of IL on the MW have also been investigated. Through structural optimization, the DF-RFeFET demonstrated a record MW value of 5.5 V among the previously reported Si FeFETs.

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Acknowledgements

This work was supported in part by the Brain Korea 21 Four Program, Korea Basic Science Institute (National Research Facilities and Equipment Center) grant funded by the Ministry of Education (grant No.2023R1A6C103A035), the Technology Innovation Program (20015909) through the Korea Evaluation Institute of Industrial Technology (KEIT), funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), Korea Basic Science Institute (National research Facilities and Equipment Center) grant funded by the Ministry of Education (grant No.2023R1A6C103A035, No.2021R1A6C101A405) and the IC Design Education Center (IDEC), Korea.

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  1. Simin Chen and Dae-Hwan Ahn have contributed equally to this work.

Authors and Affiliations

  1. Department of Photonics and Nanoelectronics, BK21 FOUR ERICA-ACE Center, Hanyang University, Ansan, 15588, Korea

    Simin Chen, Seong Ui An, Tae Hyeon Noh & Younghyun Kim

  2. Center for Opto-Electronic Materials and Devices, Korea Institute of Science and Technology (KIST), Seoul, 02792, Korea

    Dae-Hwan Ahn

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Chen, S., Ahn, DH., An, S.U. et al. TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications. J. Korean Phys. Soc. (2024). https://doi.org/10.1007/s40042-024-01079-7

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