Abstract
Atomically thin two-dimensional (2D) materials have emerged as promising candidates for flexible and transparent electronic applications. Here, we introduce non-volatile charge trapping memory devices, based on the 2D heterostructure field-effect transistor consisting of a few-layer MoS2 channel and CrPS4 charge-trapping gate stack. Clockwise hysteresis behaviors in transfer curves measured at room temperature show strong dependence on the thickness of CrPS4, which are attributed to charge trapping at trap sites in the CrPS4 layers. Our heterostructure memory device with 75 nm-thick CrPS4 layer exhibits both large memory windows up to 100 V and a high on/off current ratio (3 \(\times\) 105) with good endurance during 625 cycles because of excellent trapping ability of trap sites in the CrPS4. Especially, the memory window size can be effectively tuned from 7.6 to 100 V by changing the sweep range of gate voltage. Such high performances of the charge-trapping memory device with a simple heterostructure provide a promising route towards next-generation memory devices utilizing 2D materials.
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Acknowledgements
This work was supported by National Research Foundation of Korea (NRF) grants funded by the Korea government (MSIP) (No. 2013R1A3A2042120) and the Nano Material Technology Development Program through the NRF funded by the MSIP (No. 2016M3A7B4909668). The work at CQM and SNU was supported by the Leading Researcher Program of NRF (No. 2020R1A3B2079375). This paper was supported by Konkuk University Researcher Fund in 2019.
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Shin, M., Lee, M.J., Yoon, C. et al. Charge-trapping memory device based on a heterostructure of MoS2 and CrPS4. J. Korean Phys. Soc. 78, 816–821 (2021). https://doi.org/10.1007/s40042-021-00154-7
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DOI: https://doi.org/10.1007/s40042-021-00154-7